Circuit and method for generating a clock signal

Claim 2

A clock signal generator circuit comprising: a crystal which generates a first signal having a frequency; a drive circuit coupled to the crystal, including a first circuit having a clock signal output and which converts the first signal from the crystal to a clock signal, and a second circuit coupled to the first circuit and having a feedback signal input which applies a feedback signal to control a duty cycle of the clock signal; wherein the first circuit comprises a first field effect transistor and a second field effect transistor, the first field effect transistor having a gate, a source, and a drain, wherein the gate of the first field effect transistor is coupled to the crystal to receive the first signal, the second field effect transistor having a gate, a source, and a drain, wherein the drain of the second field effect transistor is coupled to the drain of the first field effect transistor at the clock signal output which provides the clock signal, and wherein the gate of the second field effect transistor is coupled to the crystal to receive the first signal; and a duty cycle control circuit, which is coupled between the clock signal output to receive the clock signal and the feedback signal input, and which generates the feedback signal to cause the duty cycle of the clock signal to automatically change to a steady state duty cycle.

Claim 3

The clock signal generator circuit as recited in claim 1, wherein the steady state duty cycle is adjustable to a new steady state duty cycle in response to a new feedback signal.

Claim 4

The clock signal generator circuit as recited in claim 1, wherein the steady state duty cycle is fifty percent.

Claim 5

The clock generator circuit as recited in claim 1, wherein the second circuit comprises: a third field effect transistor having a gate, a source, and a drain, wherein the drain of the third field effect transistor is coupled to the source of the first field effect transistor, wherein the source of the third field effect transistor is coupled to a voltage source, and wherein the gate of the third field effect transistor is coupled to the feedback signal; and a fourth field effect transistor having a gate, a source, and a drain, wherein the source of the fourth field effect transistor is coupled to a ground, wherein the drain of the fourth field effect transistor is coupled to the source of the second field effect transistor, and wherein the gate of the fourth field effect transistor is coupled to the gate of the third field effect transistor.

Claim 6

The clock signal generator circuit as recited in claim 1, wherein the duty cycle control circuit comprises: a circuit element which generates a new feedback signal to change the steady state duty cycle to a new steady state duty cycle.

Claim 7

A clock signal generator circuit comprising: a crystal which generates a first signal having a frequency; a drive circuit coupled to the crystal, including a first circuit having a clock signal output and which converts the first signal from the crystal to a clock signal, and a second circuit coupled to the first circuit and having a feedback signal input which applies a feedback signal to control a duty cycle of the clock signal; and a duty cycle control circuit, which is coupled between the clock signal output to receive the clock signal and the feedback signal input, and which generates the feedback signal to cause the duty cycle of the clock signal to automatically change to a steady state duty cycle, wherein the duty cycle control circuit comprises an output pad for allowing a measuring instrument to determine the duty cycle.

Claim 8

A clock signal generator circuit comprising: a crystal which generates a first signal having a frequency; a drive circuit coupled to the crystal, including a first circuit having a clock signal output and which converts the first signal from the crystal to a clock signal, and a second circuit coupled to the first circuit and having a feedback signal input which applies a feedback signal to control a duty cycle of the clock signal; and a duty cycle control circuit, which is coupled between the clock signal output to receive the clock signal and the feedback signal input, and which generates the feedback signal to cause the duty cycle of the clock signal to automatically change to a steady state duty cycle, wherein the duty cycle control circuit comprises an output pad for allowing a measuring instrument to determine the duty cycle.

Claim 9

A clock signal generator circuit comprising: a crystal which generates a first signal having a frequency; a drive circuit coupled to the crystal, including a first circuit having a clock signal output and which converts the first signal from the crystal to a clock signal, and a second circuit coupled to the first circuit and having a feedback signal input which applies a feedback signal to control a duty cycle of the clock signal; and a duty cycle control circuit which is coupled to the drive circuit means for receiving the clock signal and providing the feedback signal to cause the duty cycle of the clock signal to automatically change to a steady state duty cycle, the duty cycle control circuit comprising: a first voltage divider coupled to the clock signal output including first and second resistors connected in series which produce a first output voltage at a connection point between the first and second resistors, a first transistor switch, which is coupled between the first resistor and a voltage source, and which is closed when the clock signal is in a low state, and a second transistor switch which is coupled between the second resistor and a ground and which is closed when the clock signal is in a high state; a second voltage divider including third and fourth resistors connected in series between the voltage source and the ground which produce a second output voltage at a connection point between the third and fourth resistors; and a differential amplifier having first and second inputs coupled to the first and second output voltages and an output coupled to the feedback signal input of the second circuit, wherein the first and second voltage dividers and the differential amplifier produce the feedback signal to cause the duty cycle of the clock signal to automatically change to the steady state duty cycle.

Claim 10

A clock signal generator circuit comprising: a crystal which generates a first signal having a frequency; a drive circuit coupled to the crystal, including a first circuit having a clock signal output and which converts the first signal from the crystal to a clock signal, and a second circuit coupled to the first circuit and having a feedback signal input which applies a feedback signal to control a duty cycle of the clock signal; and a duty cycle control circuit which is coupled to the drive circuit means for receiving the clock signal and providing the feedback signal to cause the duty cycle of the clock signal to automatically change to a steady state duty cycle, the duty cycle control circuit comprising: a first voltage divider coupled to the clock signal output including first and second resistors connected in series which produce a first output voltage at a connection point between the first and second resistors, a first transistor switch, which is coupled between the first resistor and a voltage source, and which is closed when the clock signal is in a low state, and a second transistor switch which is coupled between the second resistor and a ground and which is closed when the clock signal is in a high state; a second voltage divider including third and fourth resistors connected in series between the voltage source and the ground which produce a second output voltage at a connection point between the third and fourth resistors; and a differential amplifier having first and second inputs coupled to the first and second output voltages and an output coupled to the feedback signal input of the second circuit, wherein the first and second voltage dividers and the differential amplifier produce the feedback signal to cause the duty cycle of the clock signal to automatically change to the steady state duty cycle.

Claim 11

The clock generator as recited in claim 7, wherein the duty cycle control circuit further comprises: a first capacitor coupled between the connection point between the first and second resistors and the ground for removing noise from the first output signal and reducing feedback overshoot in the first output signal; and a second capacitor coupled between the connection point between the third and fourth resistors and the ground for removing noise from the second output signal and reducing feedback overshoot in the second output signal.

Claim 12

A clock generator circuit comprising: a crystal which generates a first signal having a frequency; a drive circuit coupled to the crystal, which converts the first signal to a clock signal, and which has a clock signal output and a feedback signal input, wherein the drive circuit includes a first field effect transistor having a gate, a source, and a drain, wherein the gate is coupled to the crystal; a second field effect transistor having a gate, a source, and a drain, wherein the drain of the second field effect transistor is coupled to the drain of the first field effect transistor at a connection point which provides the clock output signal, and wherein the gate is coupled to the crystal; a third field effect transistor having a gate, a source, and a drain, wherein the drain of the third field effect transistor is coupled to the source of the first field effect transistor, wherein the source of the third field effect transistor is coupled to a voltage source, and wherein the gate of the third field effect transistor is coupled to the feedback signal; and a fourth field effect transistor having a gate, a source, and a drain, wherein the source of the fourth field effect transistor is coupled to a ground, wherein the drain of the fourth field effect transistor is coupled to the source of the second field effect transistor, and wherein the gate of the fourth field effect transistor is coupled to the gate of the third field effect transistor; and a duty cycle control circuit, which is coupled between the clock signal output and the feedback signal input, and which generates the feedback signal to cause the duty cycle to automatically change to a steady state duty cycle, including a circuit element which changes the steady state duty cycle to a new steady state duty cycle.

Claim 13

A clock generator circuit comprising: a crystal which generates a first signal having a frequency; a drive circuit coupled to the crystal, which converts the first signal to a clock signal, and which has a clock signal output and a feedback signal input, wherein the drive circuit includes a first field effect transistor having a gate, a source, and a drain, wherein the gate is coupled to the crystal; a second field effect transistor having a gate, a source, and a drain, wherein the drain of the second field effect transistor is coupled to the drain of the first field effect transistor at a connection point which provides the clock output signal, and wherein the gate is coupled to the crystal; a third field effect transistor having a gate, a source, and a drain, wherein the drain of the third field effect transistor is coupled to the source of the first field effect transistor, wherein the source of the third field effect transistor is coupled to a voltage source, and wherein the gate of the third field effect transistor is coupled to the feedback signal; and a fourth field effect transistor having a gate, a source, and a drain, wherein the source of the fourth field effect transistor is coupled to a ground, wherein the drain of the fourth field effect transistor is coupled to the source of the second field effect transistor, and wherein the gate of the fourth field effect transistor is coupled to the gate of the third field effect transistor; and a duty cycle control circuit, which is coupled between the clock signal output and the feedback signal input, and which generates the feedback signal to cause the duty cycle to automatically change to a steady state duty cycle, including a circuit element which changes the steady state duty cycle to a new steady state duty cycle.

Claim 14

The clock generator as recited in claim 9, wherein the duty cycle control circuit further comprises: an output pad for allowing a measuring instrument to determine the duty cycle.

Claim 15

A clock signal generator circuit comprising: a crystal which generates a first signal having a frequency; drive circuit means coupled to the crystal for converting the first signal from the crystal to a clock signal, for receiving a feedback signal, and for varying a duty cycle of the clock signal in response to the feedback signal; and a duty cycle control circuit coupled to the drive circuit means for receiving the clock signal and providing the feedback signal to cause the duty cycle of the clock signal to automatically change to a steady state duty cycle, the duty cycle control circuit comprising: a first voltage divider including first and second resistors connected in series which provide a first output voltage at a connection point between the first and second resistors, and first and second switches which alternately provide voltage from a voltage source to the first resistor when the clock signal is in a first state and provide voltage from the second resistor to a ground when the clock signal is in a second state that is different from the first state; and feedback means for receiving the first output voltage from the first voltage divider and for generating the feedback signal used to cause the duty cycle of the clock signal to automatically change to the steady state duty cycle.

Claim 16

A clock signal generator circuit comprising: a crystal which generates a first signal having a frequency; drive circuit means coupled to the crystal for converting the first signal from the crystal to a clock signal, for receiving a feedback signal, and for varying a duty cycle of the clock signal in response to the feedback signal; and a duty cycle control circuit coupled to the drive circuit means for receiving the clock signal and providing the feedback signal to cause the duty cycle of the clock signal to automatically change to a steady state duty cycle, the duty cycle control circuit comprising: a first voltage divider including first and second resistors connected in series which provide a first output voltage at a connection point between the first and second resistors, and first and second switches which alternately provide voltage from a voltage source to the first resistor when the clock signal is in a first state and provide voltage from the second resistor to a ground when the clock signal is in a second state that is different from the first state; and feedback means for receiving the first output voltage from the first voltage divider and for generating the feedback signal used to cause the duty cycle of the clock signal to automatically change to the steady state duty cycle.

Claim 17

A clock signal generator circuit comprising: a crystal which generates a first signal having a frequency; drive circuit means coupled to the crystal for converting the first signal from the crystal to a clock signal, for receiving a feedback signal, and for varying a duty cycle of the clock signal in response to the feedback signal; and a duty cycle control circuit coupled to the drive circuit means for receiving the clock signal and providing the feedback signal to cause the duty cycle of the clock signal to automatically change to a steady state duty cycle, the duty cycle control circuit comprising: a voltage divider including first and second resistors connected in series which provide an output voltage at a connection point between the first and second resistors; switch means for coupling the voltage divider to a voltage source for use in providing a first and a second voltage independent of the amplitude of the clock signal and for switching application of voltage to the voltage divider between the first voltage when the clock signal is in a high state and the second voltage when the clock signal is in a low state; and feedback means for receiving the output voltage from the voltage divider and for generating the feedback signal used to cause the duty cycle of the clock signal to automatically change to the steady state duty cycle.

Claim 18

A clock signal generator circuit comprising: a crystal which generates a first signal having a frequency; drive circuit means coupled to the crystal for converting the first signal from the crystal to a clock signal, for receiving a feedback signal, and for varying a duty cycle of the clock signal in response to the feedback signal; and a duty cycle control circuit coupled to the drive circuit means for receiving the clock signal and providing the feedback signal to cause the duty cycle of the clock signal to automatically change to a steady state duty cycle, the duty cycle control circuit comprising: a voltage divider including first and second resistors connected in series which provide an output voltage at a connection point between the first and second resistors; switch means for coupling the voltage divider to a voltage source for use in providing a first and a second voltage independent of the amplitude of the clock signal and for switching application of voltage to the voltage divider between the first voltage when the clock signal is in a high state and the second voltage when the clock signal is in a low state; and feedback means for receiving the output voltage from the voltage divider and for generating the feedback signal used to cause the duty cycle of the clock signal to automatically change to the steady state duty cycle.