Clock synchronizing apparatus and method using frequency dependent variable delay

Claim 2

A clock signal generator for generating an output clock signal synchronized with an input clock signal having an input clock frequency, comprising: an input delay having an input to which the input clock signal is applied and further having an output at which a buffered clock signal is provided; a variable delay circuit having an input coupled to the output of the input delay and having an output at which a delayed clock signal is provided, the variable delay circuit further having a frequency controlled adjustable delay circuit to provide a first time delay based on the frequency of the buffered clock signal and further having a phase controlled adjustable delay circuit to provide a second time delay based on the phase difference between the buffered clock signal and a feedback clock signal, the feedback clock signal delayed with respect to the delayed clock signal by a model time delay, the frequency controlled adjustable delay circuit including a frequency detector having an input coupled to the output of the input delay and having an output at which a frequency reference signal is provided, the frequency detector generating the frequency reference signal indicative of the input clock frequency; a bias generator having an input coupled to the output of the frequency detector to generate a control signal having a voltage level based on the frequency reference signal, the control signal provided at an output of the bias generator; and an adjustable delay circuit having a control terminal coupled to the output of the bias generator, the adjustable delay circuit adjusting a time delay according to the voltage level of the control signal to be provided as the first time delay; and an output delay having an input coupled to the output of the variable delay circuit and an output at which the output clock signal is provided.

Claim 3

The clock signal generator of claim 1 wherein the frequency reference signal comprises a current signal having a current magnitude based on the frequency of the input clock signal and the bias generator comprises: a current latch to latch the current magnitude of the frequency reference signal; and a conversion circuit coupled to the current latch to generate a control signal having a voltage level based on the latched current magnitude.

Claim 4

The clock signal generator of claim 1 wherein the frequency reference signal comprises an analog signal indicative of the input clock frequency and the bias generator comprises: an analog-to-digital converter to convert the frequency reference signal into a digital value; a register coupled to the analog-to-digital converter to store the digital value; and a digital-to-analog converter coupled to the register to convert the digital value into a control signal having a voltage level based on the stored digital value.

Claim 5

The clock signal generator of claim 1 wherein the model time delay comprises: a first model time delay circuit having a time delay equal to a time delay of the input delay, and a second model time delay having a time delay equal to a time delay of the output delay.

Claim 6

The clock signal generator of claim 1 wherein the variable delay comprises the frequency controlled adjustable delay circuit coupled to the output of the input delay, and the phase controlled adjustable delay circuit coupled to the frequency controlled adjustable delay to receive the buffered clock signal delayed by the first time delay and provide an output clock signal delayed by the first and second time delay to the input of the output delay.

Claim 7

The clock signal generator of claim 1 wherein the variable delay comprises the phase controlled adjustable delay circuit coupled to the output of the input delay, and the frequency controlled adjustable delay circuit coupled to the phase controlled adjustable delay to receive the buffered clock signal delayed by the second time delay and provide an output clock signal delayed by the first and second time delay to the input of the output delay.

Claim 8

The clock signal generator of claim 1 wherein the output delay comprises a delay equal to a propagation delay of a data path through which data is provided to a data bus coupled to the output of the data path.

Claim 9

A clock signal generator for generating an output clock signal synchronized with an input clock signal having an input clock frequency, the delay-locked loop comprising: a frequency dependent variable delay circuit having an input at which a buffered clock signal is applied and having an output at which a first delayed clock signal is provided, the buffered clock signal having a frequency equal to the input clock frequency and skewed with respect to the input clock signal by a first phase difference, the first delayed clock signal delayed with respect to the buffered clock signal by a time delay based on the frequency of the buffered clock signal; and a phase dependent variable delay circuit having a first input coupled to the output of the frequency dependent variable delay and having an output at which a pre-skewed clock signal is provided, the pre-skewed clock signal delayed with respect to the first delayed clock signal by a time delay based on the phase difference between the buffered clock signal and a delayed version of the pre-skewed clock signal further delayed by a model time delay having an input delay portion and an output delay portion, the pre-skewed clock signal leading the output clock signal by the time delay of the output delay portion.

Claim 10

A clock signal generator for generating an output clock signal synchronized with an input clock signal having an input clock frequency, the delay-locked loop comprising: a frequency dependent variable delay circuit having an input at which a buffered clock signal is applied and having an output at which a first delayed clock signal is provided, the buffered clock signal having a frequency equal to the input clock frequency and skewed with respect to the input clock signal by a first phase difference, the first delayed clock signal delayed with respect to the buffered clock signal by a time delay based on the frequency of the buffered clock signal; and a phase dependent variable delay circuit having a first input coupled to the output of the frequency dependent variable delay and having an output at which a pre-skewed clock signal is provided, the pre-skewed clock signal delayed with respect to the first delayed clock signal by a time delay based on the phase difference between the buffered clock signal and a delayed version of the pre-skewed clock signal further delayed by a model time delay having an input delay portion and an output delay portion, the pre-skewed clock signal leading the output clock signal by the time delay of the output delay portion.

Claim 11

The clock signal generator of claim 8 wherein the frequency dependent variable delay circuit comprises: a frequency detector having an input at which the buffered clock is coupled and having an output at which a frequency reference signal is provided, the frequency reference signal generated by the frequency detector indicative of the input clock frequency; a bias generator having an input coupled to the output of the frequency detector to generate a control signal having a voltage level based on the frequency reference signal, the control signal provided at an output of the bias generator; and a variable delay circuit having a control terminal coupled to the output of the bias generator, the variable delay circuit adjusting a time delay according to the voltage level of the control signal to be the time delay of the frequency dependent variable delay.

Claim 12

The clock signal generator of claim 9 wherein the frequency reference signal comprises a current signal having a current magnitude based on the frequency of the input clock signal and the bias generator comprises: a current latch to latch the current magnitude of the frequency reference signal; and a conversion circuit coupled to the current latch to generate a control signal having a voltage level based on the latched current magnitude.

Claim 13

The clock signal generator of claim 9 wherein the frequency reference signal comprises an analog signal indicative of the input clock frequency and the bias generator comprises: an analog-to-digital converter to convert the frequency reference signal into a digital value; a register coupled to the analog-to-digital converter to store the digital value; and a digital-to-analog converter coupled to the register to convert the digital value into a control signal having a voltage level based on the stored digital value.

Claim 14

The clock signal generator of claim 8 wherein the frequency dependent variable delay circuit comprises: a frequency detector coupled to receive the buffered clock signal and having an output at which a frequency reference signal is provided, and further having a sample control terminal at which a sample control signal is applied, in response to the sample control signal, the frequency detector sampling the frequency of the buffered clock signal and generating the frequency reference signal having a characteristic indicative of the input clock frequency; a sample control circuit for generating a sample control signal to cause the frequency detector to sample the frequency of the buffered clock signal; a storage circuit for storing the characteristic of the frequency reference signal; a bias generator having an input coupled to the storage circuit to generate a control signal having a voltage level based on the stored characteristic; and a variable delay circuit having a control terminal coupled to the bias generator, the variable delay adjusting a time delay according to the voltage level of the control signal to the time delay of the frequency dependent variable delay circuit.

Claim 15

The clock signal generator of claim 12 wherein the sample control circuit comprises a counter circuit coupled to receive the buffered clock signal to count a number of clock cycles and generate the sample control signal causing the frequency detector to sample the frequency of the buffered clock signal in response to counting a threshold number of clock cycles.

Claim 16

The clock signal generator of claim 12 wherein the sample control circuit comprises a frequency divider circuit coupled to receive the buffered clock signal to generate a frequency divided clock signal applied to the frequency detector as the sample control signal causing the frequency detector to sample the frequency of the buffered clock signal.

Claim 17

A delay-locked loop for generating an output clock signal synchronized with an input clock signal, comprising: an input delay having an input at which the input clock signal is applied and an output at which a first skewed clock signal is provided; an output delay having an input at which a pre-skewed clock signal is applied and an output at which the output clock signal is provided; and a variable delay circuit having an input coupled to the output of the input delay and an output coupled to the input of the output delay to provide the pre-skewed clock signal, the variable delay circuit having a frequency dependent variable delay portion providing a time delay based on the frequency of the first skewed clock signal and further having a phase dependent variable delay portion for providing a time delay to compensate for timing skew introduced by the input delay, the frequency dependent variable delay portion, and the output delay, the frequency dependent variable delay portion including a frequency detector having an input coupled to the output of the input delay and having an output at which a frequency reference signal is provided, the frequency reference signal generated by the frequency detector indicative of an input clock frequency; a bias generator having an input coupled to the output of the frequency detector to generate a control signal having a voltage level based on the frequency reference signal, the control signal provided at an output of the bias generator; and an adjustable delay circuit having a control terminal coupled to the output of the bias generator, the adjustable delay circuit adjusting a time delay according to the voltage level of the control signal to be the time delay of the frequency dependent variable delay portion.

Claim 18

A delay-locked loop for generating an output clock signal synchronized with an input clock signal, comprising: an input delay having an input at which the input clock signal is applied and an output at which a first skewed clock signal is provided; an output delay having an input at which a pre-skewed clock signal is applied and an output at which the output clock signal is provided; and a variable delay circuit having an input coupled to the output of the input delay and an output coupled to the input of the output delay to provide the pre-skewed clock signal, the variable delay circuit having a frequency dependent variable delay portion providing a time delay based on the frequency of the first skewed clock signal and further having a phase dependent variable delay portion for providing a time delay to compensate for timing skew introduced by the input delay, the frequency dependent variable delay portion, and the output delay, the frequency dependent variable delay portion including a frequency detector having an input coupled to the output of the input delay and having an output at which a frequency reference signal is provided, the frequency reference signal generated by the frequency detector indicative of an input clock frequency; a bias generator having an input coupled to the output of the frequency detector to generate a control signal having a voltage level based on the frequency reference signal, the control signal provided at an output of the bias generator; and an adjustable delay circuit having a control terminal coupled to the output of the bias generator, the adjustable delay circuit adjusting a time delay according to the voltage level of the control signal to be the time delay of the frequency dependent variable delay portion.

Claim 19

The delay-locked loop of claim 15 wherein the frequency reference signal comprises a current signal having a current magnitude based on the frequency of the input clock signal and the bias generator comprises: a current latch to latch the current magnitude of the frequency reference signal; and a conversion circuit coupled to the current latch to generate a control signal having a voltage level based on the latched current magnitude.

Claim 20

The delay-locked loop of claim 15 wherein the frequency reference signal comprises an analog signal indicative of the input clock frequency and the bias generator comprises: an analog-to-digital converter to convert the frequency reference signal into a digital value; a register coupled to the analog-to-digital converter to store the digital value; and a digital-to-analog converter coupled to the register to convert the digital value into a control signal having a voltage level based on the stored digital value.

Claim 21

The delay-locked loop of claim 15 wherein the variable delay circuit comprises the frequency dependent variable delay portion coupled to the output of the input delay, and the phase controlled adjustable delay circuit coupled to the frequency dependent variable delay portion to receive the first skewed clock signal delayed by the frequency dependent variable delay portion and provide the pre-skewed clock signal to the output delay.

Claim 22

The delay-locked loop of claim 15 wherein the variable delay comprises the phase dependent variable delay portion coupled to the output of the input delay, and the frequency dependent variable delay portion coupled to the phase dependent variable delay portion to receive the first skewed clock signal delayed by the phase dependent variable delay portion and provide the pre-skewed clock signal to the output delay.

Claim 23

The delay-locked loop of claim 15 wherein the output delay comprises a delay equal to a propagation delay of a data path through which data is provided to a data bus coupled to the output of the data path.

Claim 24

A delay-locked loop for providing an output clock signal synchronized with an input clock signal having an input clock frequency, the delay-locked loop comprising: an input delay having an input at which the input clock signal is applied and having an output at which a buffered clock signal is provided; a variable delay line having an input coupled to the output of the input delay and having an output at which a delayed clock signal is provided, the variable delay line further having a first adjustable delay portion to provide a first time delay based on a first control signal and a second adjustable delay portion to provide a second time delay based on a second control signal; an output delay having an input coupled to the output of the variable delay line and having an output at which the output clock signal is provided; a frequency detector having an input coupled to the output of the input delay and an output coupled to the first adjustable delay portion of the variable delay line to provide a frequency reference signal indicative of the input clock frequency as the first control signal; a model delay having an input coupled to the output of the variable delay line and an output at which a feedback clock signal is provided; and a phase detector having a first input coupled to the output of the input delay and a second input coupled to the output of the model delay, the phase detector generating a reference phase signal indicative of the phase difference between the feedback clock signal and the buffered clock signal to be provided to the second adjustable delay portion of the variable delay line as the second control signal.

Claim 25

A delay-locked loop for providing an output clock signal synchronized with an input clock signal having an input clock frequency, the delay-locked loop comprising: an input delay having an input at which the input clock signal is applied and having an output at which a buffered clock signal is provided; a variable delay line having an input coupled to the output of the input delay and having an output at which a delayed clock signal is provided, the variable delay line further having a first adjustable delay portion to provide a first time delay based on a first control signal and a second adjustable delay portion to provide a second time delay based on a second control signal; an output delay having an input coupled to the output of the variable delay line and having an output at which the output clock signal is provided; a frequency detector having an input coupled to the output of the input delay and an output coupled to the first adjustable delay portion of the variable delay line to provide a frequency reference signal indicative of the input clock frequency as the first control signal; a model delay having an input coupled to the output of the variable delay line and an output at which a feedback clock signal is provided; and a phase detector having a first input coupled to the output of the input delay and a second input coupled to the output of the model delay, the phase detector generating a reference phase signal indicative of the phase difference between the feedback clock signal and the buffered clock signal to be provided to the second adjustable delay portion of the variable delay line as the second control signal.

Claim 26

The delay-locked loop of claim 21 wherein the first adjustable delay portion of the variable delay line comprises: a frequency detector having an input coupled to the output of the input delay and having an output at which a frequency reference signal is provided, the frequency detector generating the frequency reference signal indicative of the input clock frequency; a bias generator having an input coupled to the output of the frequency detector to generate a control signal having a voltage level based on the frequency reference signal, the control signal provided at an output of the bias generator; and a variable delay circuit having a control terminal coupled to the output of the bias generator, the variable delay adjusting a time delay according to the voltage level of the control signal to be the first time delay.

Claim 27

The delay-locked loop of claim 22 wherein the frequency reference signal comprises a current signal having a current magnitude based on the frequency of the input clock signal and the bias generator comprises: a current latch to latch the current magnitude of the frequency reference signal; and a conversion circuit coupled to the current latch to generate a control signal having a voltage level based on the latched current magnitude.

Claim 28

The delay-locked loop of claim 22 wherein the frequency reference signal comprises an analog signal indicative of the input block frequency and the bias generator comprises: an analog-to-digital converter to convert the frequency reference signal into a digital value; a register coupled to the analog-to-digital converter to store the digital value; and a digital-to-analog converter coupled to the register to convert the digital value into a control signal having a voltage level based on the stored digital value.

Claim 29

The delay-locked loop of claim 21 wherein the first adjustable delay portion of the variable delay line comprises: a frequency detector having an input coupled to the output of the input delay, having an output at which a frequency reference signal is provided, and further having a sample control terminal at which a sample control signal is applied, in response to the sample control signal, the frequency detector sampling the frequency of the buffered clock signal and generating the frequency reference signal having a characteristic indicative of the input clock frequency; a sample control circuit for generating a sample control signal to cause the frequency detector to sample the frequency of the buffered clock signal; a storage circuit for storing the characteristic of the frequency reference signal; a bias generator having an input coupled to the storage circuit to generate a control signal having a voltage level based on the stored characteristic; and a variable delay circuit having a control terminal coupled to the bias generator, the variable delay adjusting a time delay according to the voltage level of the control signal to be the first time delay.

Claim 30

The delay-locked loop of claim 25 wherein the sample control circuit comprises a counter circuit coupled to the output of the input delay to count a number of clock cycles and generate a sample control signal causing the frequency detector to sample the frequency of the buffered clock signal in response to counting a threshold number of clock cycles.

Claim 31

The delay-locked loop of claim 25 wherein the sample control circuit comprises a frequency divider circuit coupled to the output of the input delay to generate a frequency divided clock signal applied to the frequency detector as the sample control signal causing the frequency detector to sample the frequency of the buffered clock signal.

Claim 32

The delay-locked loop of claim 21 wherein the model time delay comprises: a first model time delay circuit having a time delay equal to a time delay of the input delay, and a second model time delay having a time delay equal to a time delay of the output delay.

Claim 33

The delay-locked loop of claim 21 wherein the variable delay line comprises the first adjustable delay portion coupled to the output of the input buffer, and the second adjustable delay portion coupled to the first adjustable delay portion to receive the buffered clock signal delayed by the first time delay and provide a clock signal delayed by the first and second time delays.

Claim 34

The delay-locked loop of claim 21 wherein the variable delay line comprises the second adjustable delay portion coupled to the output of the input buffer, and the first adjustable delay portion coupled to the second adjustable delay portion to receive the buffered clock signal delayed by the second time delay and provide a clock signal delayed by the first and second time delays.

Claim 35

The delay-locked loop of claim 21 wherein the output delay comprises a delay equal to a propagation delay of a data path through which data is provided to a data bus coupled to the output of the data path.

Claim 36

A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; a delay-locked loop coupled to at least the control circuit and adapted to receive an input clock signal, the delay-locked loop generating an output clock signal synchronized with the input clock signal, the delay-locked loop comprising: an input delay having an input at which the input clock signal is applied and an output at which a first skewed clock signal is provided; an output delay having an input at which a pre-skewed clock signal is applied and an output at which the output clock signal is provided; and a variable delay circuit having an input coupled to the output of the input delay and an output coupled to the input of the output delay to provide the pre-skewed clock signal, the variable delay circuit having a frequency dependent variable delay portion providing a time delay based on the frequency of the first skewed clock signal and further having a phase dependent variable delay portion for providing a time delay to compensate for timing skew introduced by the input delay, the frequency dependent variable delay portion, and the output delay.

Claim 37

A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; a delay-locked loop coupled to at least the control circuit and adapted to receive an input clock signal, the delay-locked loop generating an output clock signal synchronized with the input clock signal, the delay-locked loop comprising: an input delay having an input at which the input clock signal is applied and an output at which a first skewed clock signal is provided; an output delay having an input at which a pre-skewed clock signal is applied and an output at which the output clock signal is provided; and a variable delay circuit having an input coupled to the output of the input delay and an output coupled to the input of the output delay to provide the pre-skewed clock signal, the variable delay circuit having a frequency dependent variable delay portion providing a time delay based on the frequency of the first skewed clock signal and further having a phase dependent variable delay portion for providing a time delay to compensate for timing skew introduced by the input delay, the frequency dependent variable delay portion, and the output delay.

Claim 38

The memory device of claim 32 wherein the frequency dependent variable delay portion of the delay-locked loop comprises: a frequency detector having an input coupled to the output of the input delay and having an output at which a frequency reference signal is provided, the frequency reference signal generated by the frequency detector indicative of an input clock frequency; a bias generator having an input coupled to the output of the frequency detector to generate a control signal having a voltage level based on the frequency reference signal, the control signal provided at an output of the bias generator; and an adjustable delay circuit having a control terminal coupled to the output of the bias generator, the adjustable delay circuit adjusting a time delay according to the voltage level of the control signal to be the time delay of the frequency dependent variable delay portion.

Claim 39

The delay-locked loop of claim 33 wherein the frequency reference signal comprises a current signal having a current magnitude based on the frequency of the input clock signal and the bias generator comprises: a current latch to latch the current magnitude of the frequency reference signal; and a conversion circuit coupled to the current latch to generate a control signal having a voltage level based on the latched current magnitude.

Claim 40

The delay-locked loop of claim 33 wherein the frequency reference signal comprises an analog signal indicative of the input clock frequency and the bias generator comprises: an analog-to-digital converter to convert the frequency reference signal into a digital value; a register coupled to the analog-to-digital converter to store the digital value; and a digital-to-analog converter coupled to the register to convert the digital value into a control signal having a voltage level based on the stored digital value.

Claim 41

The memory device of claim 32 wherein the frequency dependent variable delay portion of the delay-locked loop comprises: a frequency detector having an input coupled to the output of the input delay circuit, having an output at which a frequency reference signal is provided, and further having a sample control terminal at which a sample control signal is applied, in response to the sample control signal, the frequency detector sampling the frequency of the buffered clock signal and generating the frequency reference signal having a characteristic indicative of the input clock frequency; a sample control circuit for generating a sample control signal to cause the frequency detector to sample the frequency of the buffered clock signal; a storage circuit for storing the characteristic of the frequency reference signal; a bias generator having an input coupled to the storage circuit to generate a control signal having a voltage level based on the stored characteristic; and an adjustable delay circuit having a control terminal coupled to the bias generator, the adjustable delay circuit adjusting a time delay according to the voltage level of the control signal to be provided as the first time delay.

Claim 42

The memory device of claim 32 wherein the variable delay circuit of the delay-locked loop comprises the frequency dependent variable delay portion coupled to the output of the input delay, and the phase controlled adjustable delay circuit coupled to the frequency dependent variable delay portion to receive the first skewed clock signal delayed by the frequency dependent variable delay portion and provide the pre-skewed clock signal to the output delay.

Claim 43

The memory device of claim 32 wherein the variable delay circuit of the delay-locked loop comprises the phase dependent variable delay portion coupled to the output of the input delay, and the frequency dependent variable delay portion coupled to the phase dependent variable delay portion to receive the first skewed clock signal delayed by the phase dependent variable delay portion and provide the pre-skewed clock signal to the output delay.

Claim 44

The memory device of claim 32 wherein the output delay of the delay-locked loop comprises a delay equal to a propagation delay of a data path through which data is provided to a data bus coupled to the output of the data path.

Claim 45

A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; a clock signal generator coupled to at least the control circuit and adapted to receive an input clock signal, the clock signal generator generating an output clock signal synchronized with the input clock signal having an input clock frequency, the clock signal generator comprising: a frequency dependent variable delay circuit having an input at which a buffered clock signal is applied and having an output at which a first delayed clock signal is provided, the buffered clock signal having a frequency equal to the input clock frequency and skewed with respect to the input clock signal by a first phase difference, the first delayed clock signal delayed with respect to the buffered clock signal by a time delay based on the frequency of the buffered clock signal; and a phase dependent variable delay circuit having a first input coupled to the output of the frequency dependent variable delay and having an output at which a pre-skewed clock signal is provided, the pre-skewed clock signal delayed with respect to the first delayed clock signal by a time delay based on the phase difference between the buffered clock signal and a delayed version of the pre-skewed clock signal further delayed by a model time delay having an input delay portion and an output delay portion, the pre-skewed clock signal leading the output clock signal by the time delay of the output delay portion.

Claim 46

A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; a clock signal generator coupled to at least the control circuit and adapted to receive an input clock signal, the clock signal generator generating an output clock signal synchronized with the input clock signal having an input clock frequency, the clock signal generator comprising: a frequency dependent variable delay circuit having an input at which a buffered clock signal is applied and having an output at which a first delayed clock signal is provided, the buffered clock signal having a frequency equal to the input clock frequency and skewed with respect to the input clock signal by a first phase difference, the first delayed clock signal delayed with respect to the buffered clock signal by a time delay based on the frequency of the buffered clock signal; and a phase dependent variable delay circuit having a first input coupled to the output of the frequency dependent variable delay and having an output at which a pre-skewed clock signal is provided, the pre-skewed clock signal delayed with respect to the first delayed clock signal by a time delay based on the phase difference between the buffered clock signal and a delayed version of the pre-skewed clock signal further delayed by a model time delay having an input delay portion and an output delay portion, the pre-skewed clock signal leading the output clock signal by the time delay of the output delay portion.

Claim 47

The memory device of claim 40 wherein the frequency dependent variable delay circuit of the clock signal generator comprises: a frequency detector having an input at which the buffered clock is coupled and having an output at which a frequency reference signal is provided, the frequency reference signal generated by the frequency detector indicative of the input clock frequency; a bias generator having an input coupled to the output of the frequency detector to generate a control signal having a voltage level based on the frequency reference signal, the control signal provided at an output of the bias generator; and a variable delay circuit having a control terminal coupled to the output of the bias generator, the variable delay circuit adjusting a time delay according to the voltage level of the control signal to be the time delay of the frequency dependent variable delay.

Claim 48

The memory device of claim 41 wherein the frequency reference signal comprises a current signal having a current magnitude based on the frequency of the input clock signal and the bias generator comprises: a current latch to latch the current magnitude of the frequency reference signal; and a conversion circuit coupled to the current latch to generate a control signal having a voltage level based on the latched current magnitude.

Claim 49

The memory device of claim 41 wherein the frequency reference signal comprises an analog signal indicative of the input clock frequency and the bias generator comprises: an analog-to-digital converter to convert the frequency reference signal into a digital value; a register coupled to the analog-to-digital converter to store the digital value; and a digital-to-analog converter coupled to the register to convert the digital value into a control signal having a voltage level based on the stored digital value.

Claim 50

The memory device of claim 40 wherein the frequency dependent variable delay circuit of the clock signal generator comprises: a frequency detector coupled to receive the buffered clock signal and having an output at which a frequency reference signal is provided, and further having a sample control terminal at which a sample control signal is applied, in response to the sample control signal, the frequency detector sampling the frequency of the buffered clock signal and generating the frequency reference signal having a characteristic indicative of the input clock frequency; a sample control circuit for generating a sample control signal to cause the frequency detector to sample the frequency of the buffered clock signal; a storage circuit for storing the characteristic of the frequency reference signal; a bias generator having an input coupled to the storage circuit to generate a control signal having a voltage level based on the stored characteristic; and a variable delay circuit having a control terminal coupled to the bias generator, the variable delay adjusting a time delay according to the voltage level of the control signal to the time delay of the frequency dependent variable delay circuit.

Claim 51

A computer system, comprising: a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device coupled to the processor, the memory device comprising, an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; a delay-locked loop coupled to at least the control circuit and adapted to receive an input clock signal, the delay-locked loop generating an output clock signal synchronized with the input clock signal, the delay-locked loop comprising: an input delay having an input at which the input clock signal is applied and an output at which a first skewed clock signal is provided; an output delay having an input at which a pre-skewed clock signal is applied and an output at which the output clock signal is provided; and a variable delay circuit having an input coupled to the output of the input delay and an output coupled to the input of the output delay to provide the pre-skewed clock signal, the variable delay circuit having a frequency dependent variable delay portion providing a time delay based on the frequency of the first skewed clock signal and further having a phase dependent variable delay portion for providing a time delay to compensate for timing skew introduced by the input delay, the frequency dependent variable delay portion, and the output delay.

Claim 52

A computer system, comprising: a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device coupled to the processor, the memory device comprising, an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; a delay-locked loop coupled to at least the control circuit and adapted to receive an input clock signal, the delay-locked loop generating an output clock signal synchronized with the input clock signal, the delay-locked loop comprising: an input delay having an input at which the input clock signal is applied and an output at which a first skewed clock signal is provided; an output delay having an input at which a pre-skewed clock signal is applied and an output at which the output clock signal is provided; and a variable delay circuit having an input coupled to the output of the input delay and an output coupled to the input of the output delay to provide the pre-skewed clock signal, the variable delay circuit having a frequency dependent variable delay portion providing a time delay based on the frequency of the first skewed clock signal and further having a phase dependent variable delay portion for providing a time delay to compensate for timing skew introduced by the input delay, the frequency dependent variable delay portion, and the output delay.

Claim 53

The computer system of claim 45 wherein the frequency dependent variable delay portion of the delay-locked loop comprises: a frequency detector having an input coupled to the output of the input delay and having an output at which a frequency reference signal is provided, the frequency reference signal generated by the frequency detector indicative of an input clock frequency; a bias generator having an input coupled to the output of the frequency detector to generate a control signal having a voltage level based on the frequency reference signal, the control signal provided at an output of the bias generator; and an adjustable delay circuit having a control terminal coupled to the output of the bias generator, the adjustable delay circuit adjusting a time delay according to the voltage level of the control signal to be the time delay of the frequency dependent variable delay portion.

Claim 54

The computer system of claim 46 wherein the frequency reference signal comprises a current signal having a current magnitude based on the frequency of the input clock signal and the bias generator comprises: a current latch to latch the current magnitude of the frequency reference signal; and a conversion circuit coupled to the current latch to generate a control signal having a voltage level based on the latched current magnitude.

Claim 55

The computer system of claim 46 wherein the frequency reference signal comprises an analog signal indicative of the input clock frequency and the bias generator comprises: an analog-to-digital converter to convert the frequency reference signal into a digital value; a register coupled to the analog-to-digital converter to store the digital value; and a digital-to-analog converter coupled to the register to convert the digital value into a control signal having a voltage level based on the stored digital value.

Claim 56

The computer system of claim 45 wherein the frequency dependent variable delay portion of the delay-locked loop comprises: a frequency detector having an input coupled to the output of the input delay circuit, having an output at which a frequency reference signal is provided, and further having a sample control terminal at which a sample control signal is applied, in response to the sample control signal, the frequency detector sampling the frequency of the buffered clock signal and generating the frequency reference signal having a characteristic indicative of the input clock frequency; a sample control circuit for generating a sample control signal to cause the frequency detector to sample the frequency of the buffered clock signal; a storage circuit for storing the characteristic of the frequency reference signal; a bias generator having an input coupled to the storage circuit to generate a control signal having a voltage level based on the stored characteristic; and an adjustable delay circuit having a control terminal coupled to the bias generator, the adjustable delay circuit adjusting a time delay according to the voltage level of the control signal to be provided as the first time delay.

Claim 57

The computer system of claim 45 wherein the variable delay circuit of the delay-locked loop comprises the frequency dependent variable delay portion coupled to the output of the input delay, and the phase controlled adjustable delay circuit coupled to the frequency dependent variable delay portion to receive the first skewed clock signal delayed by the frequency dependent variable delay portion and provide the pre-skewed clock signal to the output delay.

Claim 58

The computer system of claim 45 wherein the variable delay circuit of the delay-locked loop comprises the phase dependent variable delay portion coupled to the output of the input delay, and the frequency dependent variable delay portion coupled to the phase dependent variable delay portion to receive the first skewed clock signal delayed by the phase dependent variable delay portion and provide the pre-skewed clock signal to the output delay.

Claim 59

The computer system of claim 45 wherein the output delay of the delay-locked loop comprises a delay equal to a propagation delay of a data path through which data is provided to a data bus coupled to the output of the data path.

Claim 60

A computer system, comprising: a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device coupled to the processor, the memory device comprising, an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; a clock signal generator coupled to at least the control circuit and adapted to receive an input clock signal, the clock signal generator generating an output clock signal synchronized with the input clock signal having an input clock frequency, the clock signal generator comprising: a frequency dependent variable delay circuit having an input at which a buffered clock signal is applied and having an output at which a first delayed clock signal is provided, the buffered clock signal having a frequency equal to the input clock frequency and skewed with respect to the input clock signal by a first phase difference, the first delayed clock signal delayed with respect to the buffered clock signal by a time delay based on the frequency of the buffered clock signal; and a phase dependent variable delay circuit having a first input coupled to the output of the frequency dependent variable delay and having an output at which a pre-skewed clock signal is provided, the pre-skewed clock signal delayed with respect to the first delayed clock signal by a time delay based on the phase difference between the buffered clock signal and a delayed version of the pre-skewed clock signal further delayed by a model time delay having an input delay portion and an output delay portion, the pre-skewed clock signal leading the output clock signal by the time delay of the output delay portion.

Claim 61

A computer system, comprising: a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device coupled to the processor, the memory device comprising, an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a control circuit coupled to the control bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; a clock signal generator coupled to at least the control circuit and adapted to receive an input clock signal, the clock signal generator generating an output clock signal synchronized with the input clock signal having an input clock frequency, the clock signal generator comprising: a frequency dependent variable delay circuit having an input at which a buffered clock signal is applied and having an output at which a first delayed clock signal is provided, the buffered clock signal having a frequency equal to the input clock frequency and skewed with respect to the input clock signal by a first phase difference, the first delayed clock signal delayed with respect to the buffered clock signal by a time delay based on the frequency of the buffered clock signal; and a phase dependent variable delay circuit having a first input coupled to the output of the frequency dependent variable delay and having an output at which a pre-skewed clock signal is provided, the pre-skewed clock signal delayed with respect to the first delayed clock signal by a time delay based on the phase difference between the buffered clock signal and a delayed version of the pre-skewed clock signal further delayed by a model time delay having an input delay portion and an output delay portion, the pre-skewed clock signal leading the output clock signal by the time delay of the output delay portion.

Claim 62

The computer system of claim 53 wherein the frequency dependent variable delay circuit of the clock signal generator comprises: a frequency detector having an input at which the buffered clock is coupled and having an output at which a frequency reference signal is provided, the frequency reference signal generated by the frequency detector indicative of the input clock frequency; a bias generator having an input coupled to the output of the frequency detector to generate a control signal having a voltage level based on the frequency reference signal, the control signal provided at an output of the bias generator; and a variable delay circuit having a control terminal coupled to the output of the bias generator, the variable delay circuit adjusting a time delay according to the voltage level of the control signal to be the time delay of the frequency dependent variable delay.

Claim 63

The computer system of claim 54 wherein the frequency reference signal comprises a current signal having a current magnitude based on the frequency of the input clock signal and the bias generator comprises: a current latch to latch the current magnitude of the frequency reference signal; and a conversion circuit coupled to the current latch to generate a control signal having a voltage level based on the latched current magnitude.

Claim 64

The computer system of claim 54 wherein the frequency reference signal comprises an analog signal indicative of the input clock frequency and the bias generator comprises: an analog-to-digital converter to convert the frequency reference signal into a digital value; a register coupled to the analog-to-digital converter to store the digital value; and a digital-to-analog converter coupled to the register to convert the digital value into a control signal having a voltage level based on the stored digital value.

Claim 65

The computer system of claim 51 wherein the frequency dependent variable delay circuit of the clock signal generator comprises: a frequency detector coupled to receive the buffered clock signal and having an output at which a frequency reference signal is provided, and further having a sample control terminal at which a sample control signal is applied, in response to the sample control signal, the frequency detector sampling the frequency of the buffered clock signal and generating the frequency reference signal having a characteristic indicative of the input clock frequency; a sample control circuit for generating a sample control signal to cause the frequency detector to sample the frequency of the buffered clock signal; a storage circuit for storing the characteristic of the frequency reference signal; a bias generator having an input coupled to the storage circuit to generate a control signal having a voltage level based on the stored characteristic; and a variable delay circuit having a control terminal coupled to the bias generator, the variable delay adjusting a time delay according to the voltage level of the control signal to the time delay of the frequency dependent variable delay circuit.

Claim 68

The method of claim 58 wherein generating a delay control signal comprises generating a bias signal having a voltage level indicative of the frequency of the input buffered clock signal and adjusting a variable delay comprises adjusting an impedance of a voltage controlled impedance device coupling a delay circuit to a power supply.

Claim 71

The method of claim 60 wherein generating a delay control signal comprises generating a bias signal having a voltage level indicative of the frequency of the input buffered clock signal and adjusting a variable delay comprises adjusting an impedance of a voltage controlled impedance device coupling a delay circuit to a power supply.

Claim 72

The method of claim 60 wherein delaying the input buffered clock signal by the second time delay occurs before delaying the input buffered clock signal by the first time delay.

Claim 73

The method of claim 60 wherein delaying the input buffered clock signal by the first time delay occurs before delaying the input buffered clock signal by the second time delay.

Claim 76

The method of claim 64 wherein generating a delay control signal comprises generating a bias signal having a voltage level indicative of the frequency of the input buffered clock signal and adjusting a variable delay comprises adjusting an impedance of a voltage controlled impedance device coupling a delay circuit to a power supply.