Vertical panning for interlaced video

Claim 2

A vertical panning system, comprising: means for supplying respective signals having a vertical synchronizing frequency, a horizontal synchronizing frequency and a multiple of said horizontal synchronizing frequency; a horizontal display control circuit for a video display, responsive to said supplied horizontal synchronizing frequency signal for displaying a video signal by interlacing fields; a plurality of digital counting means responsive to said supplied multiple horizontal synchronizing frequency signal, said supplied vertical synchronizing frequency signal and to a panning control signal; means for decoding an output of one of said counting means and generating a second vertical synchronizing frequency signal delayed in phase relative to said supplied vertical synchronizing frequency signal by any one of a plurality of delays differing in increments corresponding in duration to horizontal half line intervals; and, a vertical display control circuit for said video display, responsive to said second vertical synchronizing frequency signal.

Claim 3

The system of claim 1, comprising means for presetting one of said digital counting means.

Claim 4

The system of claim 1, wherein said plurality of digital counting means comprises: first digital counting means for generating a first clock output signal, clocked by said multiple horizontal frequency signal and enabled by said vertical frequency signal; second digital counting means for generating a second clock output signal, clocked by said multiple horizontal frequency signal and set by said first output signal; and, third digital counting means, clocked by said vertical frequency signal, for generating a third clock output signal for presetting said second counter, said third clock output signal varying responsive to said panning control signal.

Claim 5

The system of claim 3, wherein said decoding means comprises digital decoding means responsive to said second clock output signal for generating said phase delayed vertical frequency synchronizing signal.

Claim 6

A vertical panning system, comprising: means for supplying respective signals having a vertical synchronizing frequency, a horizontal synchronizing frequency and a multiple of said horizontal synchronizing frequency; a horizontal display control circuit for a video display, responsive to said supplied horizontal synchronizing frequency signal for displaying a video signal by interlacing fields; first digital counting means for generating a first clock output signal, clocked by said multiple horizontal frequency signal and enabled by said vertical frequency signal; second digital counting means for generating a second clock output signal, clocked by said multiple horizontal frequency signal and set by said first output signal; third digital counting means, clocked by said vertical frequency signal, for generating a third clock output signal for presetting said second counter, said third clock output signal varying responsive to is said panning control signal; digital decoding means responsive to said second clock output signal for generating said phase delayed vertical frequency synchronizing signal; and, a vertical display control circuit for said video display, responsive to said second vertical synchronizing frequency signal.

Claim 7

A vertical panning system, comprising: means for supplying respective signals having a vertical synchronizing frequency, a horizontal synchronizing frequency and a multiple of said horizontal synchronizing frequency; a horizontal display control circuit for a video display, responsive to said supplied horizontal synchronizing frequency signal for displaying a video signal by interlacing fields; first digital counting means for generating a first clock output signal, clocked by said multiple horizontal frequency signal and enabled by said vertical frequency signal; second digital counting means for generating a second clock output signal, clocked by said multiple horizontal frequency signal and set by said first output signal; third digital counting means, clocked by said vertical frequency signal, for generating a third clock output signal for presetting said second counter, said third clock output signal varying responsive to is said panning control signal; digital decoding means responsive to said second clock output signal for generating said phase delayed vertical frequency synchronizing signal; and, a vertical display control circuit for said video display, responsive to said second vertical synchronizing frequency signal.

Claim 8

The system of claim 1, wherein said horizontal synchronizing frequency corresponds to a horizontal synchronizing signal of an input video signal and said multiple of said horizontal synchronizing frequency is twice that of said horizontal synchronizing signal of said input video signal.

Claim 9

The system of claim 1, wherein said video display has a wide format display ratio.

Claim 10

A vertical panning system, comprising: a source of respective signals having a vertical synchronizing frequency, a horizontal synchronizing frequency and a multiple of said horizontal synchronizing frequency; a video display having a mode of operation in which fields of an input video signal are displayed in an interlaced format; a horizontal display control circuit coupled to said video display and responsive to said supplied horizontal synchronizing frequency signal; a digital phase delay circuit, having a plurality of digital counters responsive to said supplied multiple horizontal synchronizing frequency signal, said supplied vertical synchronizing frequency signal and to a panning control signal, and having a digital decoder for an output of one of said digital counter, said digital decoder generating a second vertical synchronizing frequency signal delayed in phase relative to said supplied vertical synchronizing frequency signal by any one of a plurality of delays differing in increments corresponding in duration to horizontal half line intervals; and, a vertical display control circuit coupled to said video display and responsive to said second vertical synchronizing frequency signal.

Claim 11

A vertical panning system, comprising: a source of respective signals having a vertical synchronizing frequency, a horizontal synchronizing frequency and a multiple of said horizontal synchronizing frequency; a video display having a mode of operation in which fields of an input video signal are displayed in an interlaced format; a horizontal display control circuit coupled to said video display and responsive to said supplied horizontal synchronizing frequency signal; a digital phase delay circuit, having a plurality of digital counters responsive to said supplied multiple horizontal synchronizing frequency signal, said supplied vertical synchronizing frequency signal and to a panning control signal, and having a digital decoder for an output of one of said digital counter, said digital decoder generating a second vertical synchronizing frequency signal delayed in phase relative to said supplied vertical synchronizing frequency signal by any one of a plurality of delays differing in increments corresponding in duration to horizontal half line intervals; and, a vertical display control circuit coupled to said video display and responsive to said second vertical synchronizing frequency signal.

Claim 12

A vertical panning system, comprising: a source of respective signals having a vertical synchronizing frequency, a horizontal synchronizing frequency and a multiple of said horizontal synchronizing frequency; a video display having a mode of operation in which fields of an input video signal are displayed in an interlaced format; a horizontal display control circuit coupled to said video display and responsive to said supplied horizontal synchronizing frequency signal; a first counter, clocked by said multiple horizontal synchronizing signal, enabled by said vertical synchronizing signal and generating a first clock output signal; a second counter, clocked by said multiple horizontal synchronizing signal, set by said first clock output signal to a starting count and generating a second clock output signal; a third counter, clocked by said vertical synchronizing signal and generating a third clock output signal coupled to said second counter as said starting count, said third clock output signal varying responsive to vertical panning control signals; a decoder coupled for receiving said second clock output signal and generating a decoded output signal as said phase delayed vertical frequency synchronizing signal; and, a vertical display control circuit coupled to said video display and responsive to said second vertical synchronizing frequency signal.

Claim 13

A vertical panning system, comprising: a source of respective signals having a vertical synchronizing frequency, a horizontal synchronizing frequency and a multiple of said horizontal synchronizing frequency; a video display having a mode of operation in which fields of an input video signal are displayed in an interlaced format; a horizontal display control circuit coupled to said video display and responsive to said supplied horizontal synchronizing frequency signal; a first counter, clocked by said multiple horizontal synchronizing signal, enabled by said vertical synchronizing signal and generating a first clock output signal; a second counter, clocked by said multiple horizontal synchronizing signal, set by said first clock output signal to a starting count and generating a second clock output signal; a third counter, clocked by said vertical synchronizing signal and generating a third clock output signal coupled to said second counter as said starting count, said third clock output signal varying responsive to vertical panning control signals; a decoder coupled for receiving said second clock output signal and generating a decoded output signal as said phase delayed vertical frequency synchronizing signal; and, a vertical display control circuit coupled to said video display and responsive to said second vertical synchronizing frequency signal.

Claim 14

The system of claim 8, wherein said horizontal synchronizing frequency corresponds to a horizontal synchronizing signal of an input video signal and said multiple of said horizontal synchronizing frequency is twice that of said horizontal synchronizing signal of said input video signal.

Claim 15

The system of claim 8, wherein said video display has a wide format display ratio.