Clock regulator with precision midcycle edge timing

Claim 1

A clock regulator having precision midcycle edge timing, comprising: an input clock signal having a period, a rising edge and a falling edge; time reference means responsive to the input clock signal for generating a delayed clock signal that is an integer fraction of the input clock period; and clock buffer means including a rising edge control loop coupled to the input clock and a falling edge control loop coupled to the delayed clock, the clock buffer means for driving a clock distribution means having an output clock signal that has a rising edge and a falling edge, the output clock being coupled to both the rising and falling edge control loops, the falling edge control loop responsive to the delayed clock and to the output clock for locking the falling edge of the output clock to the delayed clock to control the phase of the falling edge of the input clock signal.