US5214682A
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High resolution digitally controlled oscillator
Assignee: Philips Semiconductors Inc
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Filing: 1991-12-27
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Granted: 1993-05-25
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Expires: 2011-12-27
Abstract
Abstract A high resolution digitally controlled oscillator is in the form of a digital frequency divider, which uses calculation logic to utilize both the rising edge and the falling edge (start edge and stop edge) of the input clock pulses to provide the capability of alternating between two adjacent frequencies. This results in significantly improved resolution, since the division ratio is not dependent upon any integral number of clock periods.
Inventors
- 👤 Lawrence T. Clark
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:39
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/68
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
112 words
A high resolution digitally controlled oscillator including in combination: a source of clock pulses, each having a rising edge and a falling edge; a frequency divider circuit coupled with said source of clock pulses for providing an output signal having a changing binary state, which is predetermined division ratio of said clock pulses; and control means coupled with said frequency divider circuit for causing said frequency divider circuit to change the binary state of the output signal therefrom and therefore change the division ratio of said frequency divider circuit in response to selected ones of the rising edges and falling edges of said clock pulses to produce a high resolution output signal.
Claim 2
Dependent Claim
112 words
A high resolution digitally controlled oscillator including in combination: a source of clock pulses, each having a rising edge and a falling edge; a frequency divider circuit coupled with said source of clock pulses for providing an output signal having a changing binary state, which is predetermined division ratio of said clock pulses; and control means coupled with said frequency divider circuit for causing said frequency divider circuit to change the binary state of the output signal therefrom and therefore change the division ratio of said frequency divider circuit in response to selected ones of the rising edges and falling edges of said clock pulses to produce a high resolution output signal.
Claim 3
Dependent Claim
26 words
The combination according to claim 1 wherein said frequency divider circuit produces an output resolution at least equal to one-half the period of the clock pulses.
Claim 4
Dependent Claim
21 words
The combination according to claim 2 wherein said source of clock pulses produces clock pulses which are square-wave binary clock pulses.
Claim 5
Dependent Claim
27 words
The combination according to claim 3 wherein said frequency divider circuit has a division ratio which is a binary number with at least one binary decimal place.
Claim 6
Dependent Claim
15 words
The combination according to claim 4 wherein said binary number has two binary decimal places.
Claim 7
Dependent Claim
59 words
The combination according to claim 4 wherein said control means includes coincidence gate means responsive to the rising/falling edge of a clock pulse immediately preceding a current clock pulse, in conjunction with at least one other control signal indicative of the previous rising/falling edge of the clock signals used to produce an output signal transition from said frequency divider.
Claim 8
Dependent Claim
71 words
The combination according to claim 4 wherein the two low order bit values of the binary number, used for establishing the division ratio of said frequency divider circuit, comprise two binary decimal places, the highest order of which establishes the period of the output signal from said frequency divider, and whereas the lowest order binary decimal number is used to adjust the duty cycle of the output signal from the divider.
Claim 9
Dependent Claim
27 words
The combination according to claim 1 wherein said frequency divider circuit has a division ratio which is a binary number with at least one binary decimal place.
Claim 10
Dependent Claim
71 words
The combination according to claim 8 wherein the two low order bit values of the binary number, used for establishing the division ratio of said frequency divider circuit, comprise two binary decimal places, the highest order of which establishes the period of the output signal from said frequency divider, and whereas the lowest order binary decimal number is used to adjust the duty cycle of the output signal from the divider.
Claim 11
Dependent Claim
15 words
The combination according to claim 9 wherein said binary number has two binary decimal places.
Claim 12
Dependent Claim
59 words
The combination according to claim 1 wherein said control means includes coincidence gate means responsive to the rising/falling edge of a clock pulse immediately preceding a current clock pulse, in conjunction with at least one other control signal indicative of the previous rising/falling edge of the clock signals used to produce an output signal transition from said frequency divider.
Claim 13
Dependent Claim
21 words
The combination according to claim 11 wherein said source of clock pulses produces clock pulses which are square-wave binary clock pulses.
Claim 14
Dependent Claim
26 words
The combination according to claim 12 wherein said frequency divider circuit produces an output resolution at least equal to one-half the period of the clock pulses.
Claim 15
Dependent Claim
33 words
The combination according to claim 13 wherein the output resolution is at least equal to one-fourth the period of the clock pulses in applications not requiring a 50% duty cycle on the output.
Claim 16
Dependent Claim
127 words
A high resolution digitally controlled oscillator including in combination: a source of clock pulses, each having a rising edge and a falling edge; a frequency divider circuit coupled with said source of clock pulses for providing an output signal having a changing binary state, which is a predetermined division ratio of said clock pulses in the form of a binary number with at least two binary decimal places; and control means coupled with said frequency divider circuit for causing said frequency divider circuit to change the binary state of the output signal therefrom and therefore change the division ratio of said frequency divider circuit in response to selected ones of the rising edges and falling edges of said clock pulses to produce a high resolution output signal.
Claim 17
Dependent Claim
127 words
A high resolution digitally controlled oscillator including in combination: a source of clock pulses, each having a rising edge and a falling edge; a frequency divider circuit coupled with said source of clock pulses for providing an output signal having a changing binary state, which is a predetermined division ratio of said clock pulses in the form of a binary number with at least two binary decimal places; and control means coupled with said frequency divider circuit for causing said frequency divider circuit to change the binary state of the output signal therefrom and therefore change the division ratio of said frequency divider circuit in response to selected ones of the rising edges and falling edges of said clock pulses to produce a high resolution output signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-24 | 1996-11-23 | 1997-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-24 | 2000-11-23 | 2001-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-24 | 2004-11-23 | 2005-05-25 | $7700.00 | Window Closed / Lapsed |