US5056015A
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Architectures for serial or parallel loading of writable control store
Assignee: 3DLabs Ltd
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Filing: 1989-03-21
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Granted: 1991-10-08
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Expires: 2009-03-21
Abstract
Abstract A multiprocessor subsystem, wherein each processor is separately microcoded so that the processors can run concurrently and asynchronously. To conserve lines and provide flexibility in specifying the subsystem configuration, a serial loop interface preferably provides the data access from the higher-level processor to all of the control stores. To maximize the net bandwidth of this loop, each separate control store preferably interfaces to this serial line using a bank of serial/parallel registers which can load the instructions into the control store, or clock the instruction stream incrementally, or simply clock the instruction stream along as fast as possible. Thus, the bandwidth of this line is used efficiently, and only a minimal number of instructions is required to access control storage for a given processor. One of the processors is a numeric processing module, which is connected to a cache memory by a very wide cache bus. This processor can receive programs either over the serial loop or over the cache bus. The use of the wide cache bus for parallel microinstruction transfer permits fast microcode overlaying. This system even makes dynamic paging of microcode practical in some applications.
Inventors
- 👤 David R. Baldwin
- 👤 Malcolm E. Wilson
- 👤 Neil F. Trevett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:12
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/24
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
101 words
A multiprocessor subsystem, comprising: a plurality of processors, each connected to execute instruction sequences from a respective control store thereof; a plurality of serial/parallel registers, each having a parallel port connected to a respective one of said control stores, and each having serial input and output ports, said serial ports being connected in series to provide a serial loop interface to said plural control stores; wherein said serial/parallel registers can selectably operate in a first mode, wherein data is shifted along as rapidly as possible, and in a second mode, wherein data is loaded in parallel into said respective control store.
Claim 2
Dependent Claim
101 words
A multiprocessor subsystem, comprising: a plurality of processors, each connected to execute instruction sequences from a respective control store thereof; a plurality of serial/parallel registers, each having a parallel port connected to a respective one of said control stores, and each having serial input and output ports, said serial ports being connected in series to provide a serial loop interface to said plural control stores; wherein said serial/parallel registers can selectably operate in a first mode, wherein data is shifted along as rapidly as possible, and in a second mode, wherein data is loaded in parallel into said respective control store.
Claim 3
Dependent Claim
51 words
The multiprocessor subsystem of claim 1, wherein at least one said processor has priority on data accesses to a respective local data cache memory, and wherein said processor can load instructions into said respective control store thereof either through said serial/parallel registers from said serial loop, or from said cache memory.
Claim 4
Dependent Claim
78 words
The multiprocessor subsystem of claim 1, wherein said serial loop is configured so that every one of said serial/parallel registers has a serial port connected in series with a respective serial port of at least one other of said serial/parallel registers, through said serial interfaces thereof, and at least one of said serial/parallel registers has said serial input port thereof connected in parallel with said respective serial input port of at least one other of said serial/parallel registers.
Claim 5
Dependent Claim
82 words
The multiprocessor subsystem of claim 1, wherein a plurality of mutually similar ones of said processors are mounted on respective mutually similar expansion modules, and wherein at least some ones of said expansion modules are physically separable from other ones of said expansion modules, and wherein said serial loop is configured so that at least one said expansion module includes a serial/parallel register which is paralleled, within said serial loop, with one of said serial/parallel registers on another of said expansion modules.
Claim 6
Dependent Claim
15 words
The subsystem of claim 1, wherein said serial/parallel registers are constructed using diagnostic shift registers.
Claim 7
Dependent Claim
26 words
The subsystem of claim 1, wherein at least one of said serial/parallel registers is constructed using a plurality of diagnostic shift registers connected together in series.
Claim 8
Dependent Claim
14 words
The subsystem of claim 1, wherein said serial loop configuration includes multiple parallel branches.
Claim 9
Dependent Claim
24 words
The subsystem of claim 1, wherein said parallel ports of said serial/parallel registers each provide a read/write interface to said respective writable control store.
Claim 10
Dependent Claim
65 words
The subsystem of claim 1, further comprising microcode load control logic, which includes at least one output, connected to said respective serial input of some one of said serial/parallel registers, and at least one input, connected to said respective serial output of some other one of said serial/parallel registers; whereby said serial loop includes said microcode load control logic as well as said serial/parallel registers.
Claim 11
Dependent Claim
24 words
The subsystem of claim 1, further comprising a serial clock line connected to provide clock signals to multiple ones of said serial/parallel shift registers.
Claim 12
Dependent Claim
92 words
The subsystem of claim 1, further comprising microcode load control logic, which comprises at least one output, connected to said respective serial input of some one of said serial/parallel registers, and at least one input, connected to said respective serial output of some other one of said serial/parallel registers, connected so that said serial loop includes said microcode load control logic as well as said serial/parallel registers; said microcode load control logic also being operatively connected to an external system bus, to selectably interface said serial loop to said external system bus.
Claim 13
Dependent Claim
103 words
The subsystem of claim 1, wherein said serial loop configuration includes multiple parallel branches; and further comprising microcode load control logic, which comprises at least one output, connected to said respective serial input of some one of said serial/parallel registers, and at least one input, connected to said respective serial output of some other one of said serial/parallel registers, connected so that said serial loop includes said microcode load control logic as well as said serial/parallel registers; said microcode load control logic also comprising a return multiplexer having multiple inputs respectively connected to said serial outputs of multiple ones of said serial/parallel registers.
Claim 14
Dependent Claim
110 words
A processing system, comprising: a data cache memory; a control processor and a numeric processor, concurrently operable asynchronously; wherein said numeric processor is microcoded, and executes instructions from a writable control store; and wherein said control processor controls access to said data cache memory by said numeric processor, and can command said numeric processor to execute an instruction sequence; and wherein said numeric processor is connected to said data cache memory by a cache bus which is more than 128 lines wide, and wherein said control processor can command said numeric processor to load data received on said cache data bus into said writable control store of said numeric processor.
Claim 15
Dependent Claim
110 words
A processing system, comprising: a data cache memory; a control processor and a numeric processor, concurrently operable asynchronously; wherein said numeric processor is microcoded, and executes instructions from a writable control store; and wherein said control processor controls access to said data cache memory by said numeric processor, and can command said numeric processor to execute an instruction sequence; and wherein said numeric processor is connected to said data cache memory by a cache bus which is more than 128 lines wide, and wherein said control processor can command said numeric processor to load data received on said cache data bus into said writable control store of said numeric processor.
Claim 16
Dependent Claim
19 words
The system of claim 13, wherein said writable control store is configured to be at least 100 bits wide.
Claim 17
Dependent Claim
37 words
The system of claim 13, wherein said writable control store is configured to be at least 100 bits wide, and said cache bus is more than twice as wide as the width of said writable control store.
Claim 18
Dependent Claim
15 words
The system of claim 13, wherein said serial/parallel registers are constructed using diagnostic shift registers.
Claim 19
Dependent Claim
26 words
The system of claim 13, wherein at least one of said serial/parallel registers is constructed using a plurality of diagnostic shift registers connected together in series.
Claim 20
Dependent Claim
14 words
The system of claim 9, wherein said serial loop configuration includes multiple parallel branches.
Claim 21
Dependent Claim
24 words
The system of claim 9, further comprising a serial clock line connected to provide clock signals to multiple ones of said serial/parallel shift registers.
Claim 22
Dependent Claim
24 words
The system of claim 9, wherein said parallel ports of said serial/parallel registers each provide a read/write interface to said respective writable control store.
Claim 23
Dependent Claim
65 words
The system of claim 9, further comprising microcode load control logic, which comprises at least one output, connected to said respective serial input of some one of said serial/parallel registers, and at least one input, connected to said respective serial output of some other one of said serial/parallel registers; whereby said serial loop includes said microcode load control logic as well as said serial/parallel registers.
Claim 24
Dependent Claim
92 words
The system of claim 9, further comprising microcode load control logic, which comprises at least one output, connected to said respective serial input of some one of said serial/parallel registers, and at least one input, connected to said respective serial output of some other one of said serial/parallel registers, connected so that said serial loop includes said microcode load control logic as well as said serial/parallel registers; said microcode load control logic also being operatively connected to an external system bus, to selectably interface said serial loop to said external system bus.
Claim 25
Dependent Claim
103 words
The system of claim 9, wherein said serial loop configuration includes multiple parallel branches; and further comprising microcode load control logic, which comprises at least one output, connected to said respective serial input of some one of said serial/parallel registers, and at least one input, connected to said respective serial output of some other one of said serial/parallel registers, connected so that said serial loop includes said microcode load control logic as well as said serial/parallel registers; said microcode load control logic also comprising a return multiplexer having multiple inputs respectively connected to said serial outputs of multiple ones of said serial/parallel registers.
Claim 26
Independent Claim
205 words
A system, comprising: a data cache memory; a control processor and at least one numeric processor, concurrently operable asynchronously; said control and numeric processors each being microcoded, and each being connected to execute instructions from a respective writable control store; each of said writable control stores being connected to a parallel port of a respective serial/parallel register, each of said serial/parallel registers also having serial input and output ports, wherein multiple ones of said serial/parallel registers are interconnected together in series, by said input and output ports, to configure a serial loop; wherein said serial/parallel registers can selectably operate in a first mode, wherein data is shifted along as rapidly as possible, and in a second mode, wherein data is loaded in parallel into said respective control store; wherein said control processor controls access to said data cache memory by said numeric processor, and can command said numeric processor to execute an instruction sequence; and wherein said numeric processor is connected to said data cache memory by a cache bus which is at least 128 lines wide, and wherein said control processor can command said numeric processor to load data received on said cache data bus into said writable control store of said numeric processor.
Claim 27
Independent Claim
205 words
A system, comprising: a data cache memory; a control processor and at least one numeric processor, concurrently operable asynchronously; said control and numeric processors each being microcoded, and each being connected to execute instructions from a respective writable control store; each of said writable control stores being connected to a parallel port of a respective serial/parallel register, each of said serial/parallel registers also having serial input and output ports, wherein multiple ones of said serial/parallel registers are interconnected together in series, by said input and output ports, to configure a serial loop; wherein said serial/parallel registers can selectably operate in a first mode, wherein data is shifted along as rapidly as possible, and in a second mode, wherein data is loaded in parallel into said respective control store; wherein said control processor controls access to said data cache memory by said numeric processor, and can command said numeric processor to execute an instruction sequence; and wherein said numeric processor is connected to said data cache memory by a cache bus which is at least 128 lines wide, and wherein said control processor can command said numeric processor to load data received on said cache data bus into said writable control store of said numeric processor.
Claim 28
Dependent Claim
15 words
The system of claim 24, wherein said serial/parallel registers are constructed using diagnostic shift registers.
Claim 29
Dependent Claim
26 words
The system of claim 24, wherein at least one of said serial/parallel registers is constructed using a plurality of diagnostic shift registers connected together in series.
Claim 30
Dependent Claim
14 words
The system of claim 24, wherein said serial loop configuration includes multiple parallel branches.
Claim 31
Dependent Claim
24 words
The system of claim 24, wherein said parallel ports of said serial/parallel registers each provide a read/write interface to said respective writable control store.
Claim 32
Dependent Claim
65 words
The system of claim 24, further comprising microcode load control logic, which comprises at least one output, connected to said respective serial input of some one of said serial/parallel registers, and at least one input, connected to said respective serial output of some other one of said serial/parallel registers; whereby said serial loop includes said microcode load control logic as well as said serial/parallel registers.
Claim 33
Dependent Claim
92 words
The system of claim 24, further comprising microcode load control logic, which comprises at least one output, connected to said respective serial input of some one of said serial/parallel registers, and at least one input, connected to said respective serial output of some other one of said serial/parallel registers, connected so that said serial loop includes said microcode load control logic as well as said serial/parallel registers; said microcode load control logic also being operatively connected to an external system bus, to selectably interface said serial loop to said external system bus.
Claim 34
Dependent Claim
103 words
The system of claim 24, wherein said serial loop configuration includes multiple parallel branches; and further comprising microcode load control logic, which comprises at least one output, connected to said respective serial input of some one of said serial/parallel registers, and at least one input, connected to said respective serial output of some other one of said serial/parallel registers, connected so that said serial loop includes said microcode load control logic as well as said serial/parallel registers; said microcode load control logic also comprising a return multiplexer having multiple inputs respectively connected to said serial outputs of multiple ones of said serial/parallel registers.
Claim 35
Dependent Claim
24 words
The system of claim 24, further comprising a serial clock line connected to provide clock signals to multiple ones of said serial/parallel shift registers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-07 | 1995-04-08 | 1995-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-07 | 1999-04-08 | 1999-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-07 | 2003-04-08 | 2003-10-08 | $7700.00 | Window Closed / Lapsed |