US5337022A
Expired / Lapsed
US
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Harmonic lock detector
Assignee: Nokia Bell Labs
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Filing: 1992-11-30
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Granted: 1994-08-09
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Expires: 2012-11-30
Abstract
Abstract An integrated circuit for detecting harmonic lock of a phase-locked loop includes a frequency synthesizer for receiving a reference clock signal and for generating an oscillator clock signal. A phase generator receives the oscillator clock signal and generates a phase of the oscillator clock signal. A shift register receives as an input the reference clock signal and is clocked by the phase of the oscillator clock signal to produce an output that is a repetitive sequence of logic states. In an alternate embodiment, a harmonic decode circuit decodes the shift register output to determine which harmonic the phase-locked loop has locked onto.
Inventors
- 👤 Robert L. Pritchett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:45
CPC Classifications
H; H03; H03K; H03K4/00; H03K4/06; H03K4/08; H03K4/90; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/095; H03L2207/00; H03L2207/14; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
124 words
An integrated circuit for detecting harmonic lock of a phase-locked loop comprising: a frequency synthesizer for receiving a reference clock signal and a control signal, the frequency synthesizer for generating an oscillator clock signal defining a frequency; a phase generator for receiving the oscillator clock signal and for generating a phase of the oscillator clock signal; and a shift register for receiving the reference clock signal as an input and for receiving the phase of the oscillator clock signal as a clock signal, the shift register providing an output that is a sequence of logic states, the shift register output providing the control signal to the frequency synthesizer to change the frequency of the oscillator clock signal when the frequency synthesizer is harmonically locked.
Claim 2
Dependent Claim
124 words
An integrated circuit for detecting harmonic lock of a phase-locked loop comprising: a frequency synthesizer for receiving a reference clock signal and a control signal, the frequency synthesizer for generating an oscillator clock signal defining a frequency; a phase generator for receiving the oscillator clock signal and for generating a phase of the oscillator clock signal; and a shift register for receiving the reference clock signal as an input and for receiving the phase of the oscillator clock signal as a clock signal, the shift register providing an output that is a sequence of logic states, the shift register output providing the control signal to the frequency synthesizer to change the frequency of the oscillator clock signal when the frequency synthesizer is harmonically locked.
Claim 3
Dependent Claim
15 words
An integrated circuit as recited in claim 1, wherein the shift register is a flip-flop.
Claim 4
Dependent Claim
17 words
An integrated circuit as recited in claim 1, wherein the phase generator is a quadrature generation circuit.
Claim 5
Dependent Claim
34 words
An integrated circuit as recited in claim 1, further comprising: a first divide down counter for receiving the oscillator clock signal and for providing a divided down oscillator clock signal to the phase generator.
Claim 6
Dependent Claim
38 words
An integrated circuit as recited in claim 1, further comprising: a first divide down counter for receiving the reference clock signal and for providing a divided down reference clock signal to the frequency synthesizer and the shift register.
Claim 7
Dependent Claim
34 words
An integrated circuit as recited in claim 5, further comprising: a second divide down counter for receiving the oscillator clock signal and for providing a divided down oscillator clock signal to the phase generator.
Claim 8
Dependent Claim
39 words
An integrated circuit as recited in claim 1, further comprising: a harmonic decode circuit for receiving and decoding the sequence of logic states output from the shift register to ascertain the harmonic to which the phase-locked loop is locked.
Claim 9
Independent Claim
110 words
A system including a circuit for detecting harmonic lock of a phase-locked loop, comprising: a frequency synthesizer for receiving a reference clock signal and a control signal, the frequency synthesizer for generating a phase of an oscillator clock signal having a frequency; and a shift register for receiving the reference clock signal as an input, and for receiving the phase of the oscillator clock signal as a clock signal, the shift register providing an output that is a sequence of logic states, the shift register output providing the control signal to the frequency synthesizer to change the frequency of the oscillator clock signal when the frequency synthesizer is harmonically locked.
Claim 10
Independent Claim
110 words
A system including a circuit for detecting harmonic lock of a phase-locked loop, comprising: a frequency synthesizer for receiving a reference clock signal and a control signal, the frequency synthesizer for generating a phase of an oscillator clock signal having a frequency; and a shift register for receiving the reference clock signal as an input, and for receiving the phase of the oscillator clock signal as a clock signal, the shift register providing an output that is a sequence of logic states, the shift register output providing the control signal to the frequency synthesizer to change the frequency of the oscillator clock signal when the frequency synthesizer is harmonically locked.
Claim 11
Dependent Claim
14 words
A system as recited in claim 8, wherein the shift register is a flip-flop.
Claim 12
Dependent Claim
37 words
A system as recited in claim 8, further comprising: a first divide down counter for receiving the reference clock signal and for providing a divided down reference clock signal to the frequency synthesizer and the shift register.
Claim 13
Dependent Claim
36 words
A system as recited in claim 8, further comprising a harmonic decode circuit for decoding the sequence of logic states output from the shift register to ascertain the harmonic to which the phase-locked loop is locked.
Claim 14
Independent Claim
109 words
A method of detecting harmonic lock of a frequency generator, the frequency generator receiving a reference clock signal and a control signal, comprising the steps of: generating an oscillator clock signal defining a frequency from a reference clock signal; providing the reference clock signal as the input to a shift register; clocking the shift register with a phase of the oscillator clock signal; decoding the shift register output to ascertain whether the frequency generator is harmonically locked; and controlling the frequency of the oscillator clock signal in response to the shift register output to change the frequency of the oscillator clock signal when the frequency generator is harmonically locked.
Claim 15
Independent Claim
109 words
A method of detecting harmonic lock of a frequency generator, the frequency generator receiving a reference clock signal and a control signal, comprising the steps of: generating an oscillator clock signal defining a frequency from a reference clock signal; providing the reference clock signal as the input to a shift register; clocking the shift register with a phase of the oscillator clock signal; decoding the shift register output to ascertain whether the frequency generator is harmonically locked; and controlling the frequency of the oscillator clock signal in response to the shift register output to change the frequency of the oscillator clock signal when the frequency generator is harmonically locked.
Claim 16
Dependent Claim
24 words
A method as recited in claim 12, further comprising decoding the shift register output to ascertain to which harmonic the frequency generator is locked.
Claim 17
Dependent Claim
55 words
A method as recited in claim 12, wherein the step of providing the reference clock signal as the input to a shift register comprises the steps of: dividing down the reference clock signal to generate a divided down reference clock signal; and providing the divided reference clock signal as the input to the shift register.
Claim 18
Dependent Claim
56 words
A method as recited in claim 12, wherein the step of clocking the shift register with a phase of the oscillator clock signal, comprises the steps of: dividing down the oscillator clock signal to generate a divided down oscillator clock signal; and clocking the shift register with a phase of the divided down oscillator clock signal.
Claim 19
Dependent Claim
22 words
A method as recited in claim 15, further comprising the step of generating a phase of the divided down oscillator clock signal.
Claim 20
Dependent Claim
124 words
An integrated circuit for determining the harmonic to which a phase-locked loop is locked, comprising: a frequency synthesizer for receiving a reference clock signal and for generating an oscillator clock signal; a phase generator for receiving the oscillator clock signal and for generating a phase of the oscillator clock signal; a shift register for receiving the reference clock signal as an input and for receiving the phase of the oscillator clock signal as a clock signal, the shift register providing an output, and a harmonic decode circuit for receiving the shift register output and for decoding the shift register output to determine which harmonic a phase locked loop in the frequency synthesizer is locked, the harmonic decode circuit providing an output identifying said harmonic.
Claim 21
Dependent Claim
124 words
An integrated circuit for determining the harmonic to which a phase-locked loop is locked, comprising: a frequency synthesizer for receiving a reference clock signal and for generating an oscillator clock signal; a phase generator for receiving the oscillator clock signal and for generating a phase of the oscillator clock signal; a shift register for receiving the reference clock signal as an input and for receiving the phase of the oscillator clock signal as a clock signal, the shift register providing an output, and a harmonic decode circuit for receiving the shift register output and for decoding the shift register output to determine which harmonic a phase locked loop in the frequency synthesizer is locked, the harmonic decode circuit providing an output identifying said harmonic.
Claim 22
Dependent Claim
15 words
An integrated circuit as recited in claim 17, wherein the harmonic decode circuit is binary.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |