Digital phase lock loop circuit employing oscillator triggered at zero voltage crossing of input signal

Claim 2

Digital phase lock loop circuit comprising: a. controlled oscillator means for providing variable frequency output pulse signals; b. meaNs for counting a predetermined number of said output pulse signals; c. means for comparing the time duration of a predetermined portion of an incoming input signal with the time duration required to count said predetermined number of output pulses; d. said time duration comparison means including means for synchronously resetting said counter means and triggering said oscillator means to coincide with a zero voltage crossing of said predetermined portion of said input signal; and e. means responsive to said time duration comparison for providing correction signals to said oscillator means, said oscillator means being responsive thereto to provide an output signal at a frequency such that in subsequent time duration comparisons said time difference is substantially eliminated and said input and said output signals are in the same phase relationship at least at the beginning and end of said time comparison sequence.

Claim 3

Digital phase lock loop circuit as in claim 1 wherein said time duration comparison means includes means for converting said incoming input signal into a squarewave signal of the same frequency.

Claim 4

Digital phase lock loop circuit as in claim 2 wherein said predetermined portion of said input signal comprises one cycle thereof.

Claim 5

Digital phase lock loop circuit as in claim 3 wherein said time comparison means additionally includes means for dividing the frequency of the squarewave signal by two, whereby said time comparison is thereby made with one-half cycle of said divided square wave signal.

Claim 6

Digital phase lock loop circuit as in claim 1 wherein said counting means comprises an N-digit counter circuit.

Claim 7

Digital phase lock loop circuit as in claim 5 wherein N 1 and wherein said oscillator means comprises a variable pulse width generator.

Claim 8

Digital phase lock loop circuit as in claim 5 wherein N is an integer greater than 1, and wherein the output pulse rate, frequency is equal to N times the frequency of the input signal.

Claim 9

Digital multiplier circuit for providing N output pulses for each cycle of an input signal, where N is an integer and wherein the first output pulse for each N pulses begins coincidentally with the beginning of each cycle of the input signal, wherein the invention comprises: a. frequency controllable pulse generator means for providing output pulse signals; b. means for counting said output pulses, said counter means being responsive thereto to count up to N pulses; c. means for comparing the time duration of a predetermined portion of an input signal with the time duration required for said counter means to count N pulses; d. said time duration comparison means including means for synchronously resetting said counter means and triggering said oscillator means to coincide with a zero voltage crossing of said predetermined portion of said input signal; and e. means responsive to said time duration comparison for providing pulse rate correction signals to said pulse generator means, said pulse generator means being responsive thereto to provide output pulses as a frequency such that in subsequent time duration comparisons said time difference is substantially eliminated and the frequency of the output pulses is N times the frequency of the input signal.

Claim 10

Digital multiplier circuit for providing N output pulses for each cycle of an input signal, where N is an integer and wherein the first output pulse for each N pulses begins coincidentally with the beginning of each cycle of the input signal, wherein the invention comprises: a. frequency controllable pulse generator means for providing output pulse signals; b. means for counting said output pulses, said counter means being responsive thereto to count up to N pulses; c. means for comparing the time duration of a predetermined portion of an input signal with the time duration required for said counter means to count N pulses; d. said time duration comparison means including means for synchronously resetting said counter means and triggering said oscillator means to coincide with a zero voltage crossing of said predetermined portion of said input signal; and e. means responsive to said time duration comparison for providing pulse rate correction signals to said pulse generator means, said pulse generator means being responsive thereto to provide output pulses as a frequency such that in subsequent time duration comparisons said time difference is substantially eliminated and the frequency of the output pulses is N times the frequency of the input signal.

Claim 11

Digital phase lock loop circuit as in claim 8 wherein said time duration comparison means includes means for converting said incoming input signal into a squarewave signal of the same frequency.

Claim 12

Digital phase lock loop circuit as in claim 9 wherein said predetermined portion of said input signal comprises one cycle thereof.

Claim 13

Digital phase lock loop circuit as in claim 10 wherein said time comparison means additionally includes means for dividing the frequency of the square wave signal by two, whereby said time comparison is thereby made with one-half cycle of said divided square wave signal.