US3557308A
Expired / Lapsed
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Data synchronizing system
Assignee: General Dynamics Corp
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Filing: 1968-03-01
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Granted: 1971-01-19
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Expires: 1988-03-01
Abstract
Abstract A system is described for acquiring incoming serial data, particularly of PCM code types, and establishing synchronization between the incoming data and a local clock generator. The system includes input signal conditioning circuits which applies the incoming data to a phase lock loop containing the local clock generator. The phase lock loop includes circuits for acquiring the input data and synchronizing the local clock generator therewith in spite of low signal-to-noise ratios and the loss of a large percentage of the input data bits in transmission. The local clock generator circuits include circuits which compare the phase of the clock generator output with the phase of the incoming data bits on a maximum likelihood phase estimate basis. The local clock generator outputs are applied to detect the incoming bits and reconstruct them into a noise-free output data stream.
Inventors
- 👤 Jack F Alexander
- 👤 Peter E Mallory
- 👤 Ronald C Payne
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:49
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0332
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
45 words
A synchronization system for product output signals synchronous with an input signal, said system comprising: a. a signal controlled oscillator: b. means responsive to said input signal and signals from said oscillator for providing the control signal for said oscillator which satisfies the following equation
Claim 2
Dependent Claim
45 words
A synchronization system for product output signals synchronous with an input signal, said system comprising: a. a signal controlled oscillator: b. means responsive to said input signal and signals from said oscillator for providing the control signal for said oscillator which satisfies the following equation
Claim 3
Dependent Claim
34 words
The invention as set forth in claim 1 wherein said input signals are data signals and wherein said system includes means responsive to said output signals for detecting and reconstructing said input data signals.
Claim 4
Dependent Claim
15 words
a matched filter including an integrate and dump circuit cooperated by said timing pulses, and
Claim 5
Dependent Claim
15 words
a matched filter including an integrate and dump circuit cooperated by said timing pulses, and
Claim 6
Dependent Claim
58 words
a bit rate compensation network responsive to signals from said matched filter for providing said error signal, b. means for applying input signals to said loop; c. means in at least one of said loop and signal applying means for translating said input signals into unipolar form; and d. said timing pulses being synchronous with said input signals.
Claim 7
Dependent Claim
58 words
a bit rate compensation network responsive to signals from said matched filter for providing said error signal, b. means for applying input signals to said loop; c. means in at least one of said loop and signal applying means for translating said input signals into unipolar form; and d. said timing pulses being synchronous with said input signals.
Claim 8
Dependent Claim
45 words
The invention asset forth in claim 1 wherein said oscillator and said control signal providing means are included in a phase locked loop, said loop also including compensation means responsive to the rate of said control signal for varying the bandwidth characteristic of said loop.
Claim 9
Dependent Claim
33 words
The invention as set forth in claim 1 including input signal conditioning means for controlling the gain and average value of said periodic signal prior to application to said control signal responsive means.
Claim 10
Dependent Claim
10 words
A synchronization system comprising: a. a phase locked loop including;
Claim 11
Dependent Claim
10 words
A synchronization system comprising: a. a phase locked loop including;
Claim 12
Dependent Claim
45 words
The invention as set forth in claim 5 wherein said periodic input signals are pulses representing bits of binary data, and including bit detector means for sampling said pulses upon occurrence of said timing pulses for producing output data pulses synchronous with said timing pulses.
Claim 13
Dependent Claim
157 words
A synchronization system for periodic input signals comprising a: phase locked loop having a pair of channels to which said signals are simultaneously applied; said channels each including a matched filter and a full wave rectifier; means for applying control pulses to strobe the matched filters in each of said channels at different times; means for producing an output corresponding to the difference in the outputs from each of said channels to provide an error signal; and a variable oscillator controlled by said error signal to produce clock signals synchronous with said input signal, said oscillator also providing a signal to said control pulse applying means. 8. The invention as set forth in claim 7 wherein said periodic input signals are pulses representing a series of data bits and wherein said system includes a bit detector for receiving said input signals and said clock signals and reconstructing a series of output bits synchronous with said clock signals.
Claim 14
Dependent Claim
62 words
The invention as set forth in claim 7 wherein said matched filters in each of said channels includes an integrate and dump circuit and said oscillator has connected to its output a timing generator for providing said s control pulses to said integrate and dump circuits in each of said channels which are displaced about one-half period of said periodic input signal.
Claim 15
Dependent Claim
22 words
The invention as set forth in claim 9 wherein said channels each include a multiplier circuit having inputs from said timing generator.
Claim 16
Dependent Claim
27 words
The invention as set forth in claim 9 wherein each of said channels includes a sample and hold circuit responsive to timing pulses from said timing generator.
Claim 17
Dependent Claim
68 words
The invention as set forth in claim 11 wherein said phase locked loop includes a loop compensating network connected between said channel difference output providing means and said oscillator, said networks including a pair of channels, one being a transmission path for such output and the other containing a digital low pass filter, means for combining said network channel outputs for producing the error signal for said oscillator.
Claim 18
Dependent Claim
87 words
The invention as set forth in claim 12 wherein said digital low pass filter includes: a. a trigger circuit for producing first and second pulses indicating when the input to said filter is above or below a certain threshold level respectively; an up-down counter which is incremental by said first pulses and decremented by said second pulses; c. means for varying the length of the count of said counter; and d. digital-to-analogue converting means responsive to said count for producing said digital low pass filter channel output.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-01-18 | 1974-07-20 | 1975-01-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-01-18 | 1978-07-20 | 1979-01-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-01-18 | 1982-07-20 | 1983-01-19 | $7700.00 | Window Closed / Lapsed |