US6330197B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for linearizing a programmable delay circuit
Assignee: Credence Systems Corp
•
Filing: 2000-07-31
•
Granted: 2001-12-11
•
Expires: 2020-07-31
Abstract
Abstract A random access memory (RAM) having N addressable storage locations is addressed by input data specifying a signal delay, and the RAM reads out control data controlling the delay of a delay circuit. A linearization system automatically adjusts the value of the control data stored at each of the RAM's N addresses so that the delay provided by the delay circuit is a linear function of the value of the input data. The linearization system provides two periodic reference signals ("beat" and "clock") wherein the period PB of the beat signal and the period PC of the clock signal are related by the expression PB=PC(N+1)/N. The linearization system iteratively adjusts the control data stored at each RAM address so that when the RAM continuously reads out the control data stored at the Kth RAM address, the Kth edge of the beat signal and every Nth edge thereafter substantially coincides with an edge of the delay circuit output signal.
Inventors
- 👤 Jeffrey D. Currin
- 👤 Jacob Herbold
- 👤 Manohari Reddy
- 👤 Mark Dahl
- 👤 Philip T. Kuglin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:33
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0818
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
204 words
For a delay circuit for producing an output signal in response to an input signal with a delay controlled by control data read out of a random access memory (RAM) having a plurality of addressable storage locations, each storing data at a separate RAM address and each reading out its stored control data when addressed, a method for adjusting the control data stored in said plurality of addressable storage locations so that said delay is a linear function of the RAM address, the method comprising the steps of: a. generating a clock signal having edges occurring with a period P C and a beat signal having edges occurring with a period P B , wherein P C and P B differ; b. applying the clock signal as the input signal to the delay circuit such that said delay circuit produces said output signal in response to said clock signal; and c. for each of said addressable storage locations: c1. addressing the addressable storage location, c2. performing a phase comparison of an edge of said beat signal to an edge of said output signal, and c3. adjusting the control data stored in said addressable storage location in accordance with a result of said phase comparison.
Claim 2
Dependent Claim
204 words
For a delay circuit for producing an output signal in response to an input signal with a delay controlled by control data read out of a random access memory (RAM) having a plurality of addressable storage locations, each storing data at a separate RAM address and each reading out its stored control data when addressed, a method for adjusting the control data stored in said plurality of addressable storage locations so that said delay is a linear function of the RAM address, the method comprising the steps of: a. generating a clock signal having edges occurring with a period P C and a beat signal having edges occurring with a period P B , wherein P C and P B differ; b. applying the clock signal as the input signal to the delay circuit such that said delay circuit produces said output signal in response to said clock signal; and c. for each of said addressable storage locations: c1. addressing the addressable storage location, c2. performing a phase comparison of an edge of said beat signal to an edge of said output signal, and c3. adjusting the control data stored in said addressable storage location in accordance with a result of said phase comparison.
Claim 3
Dependent Claim
89 words
The method in accordance with claim 1 wherein step c3 comprises the substeps of: c3a. adjusting the control data stored in said addressable storage location to increase the delay of said delay circuit when said phase comparison indicates the edge of said beat signal lags the edge of said output signal, and c3b. adjusting the control data stored in said addressable storage location to decrease the delay of said delay circuit when said phase comparison indicates the edge of said beat signal leads the edge of said output signal.
Claim 4
Dependent Claim
26 words
The method in accordance with claim 1 wherein P B =P C (N+1)/N, where N is a number of said addressable storage locations of said RAM.
Claim 5
Dependent Claim
42 words
The method in accordance with claim 3 wherein step c3 comprises the step of adjusting the control data stored in said storage location so that every Nth edge of the beat signal substantially coincides with every (N+1)th edge of said output signal.
Claim 6
Independent Claim
144 words
An apparatus for generating a timing signal, the apparatus comprising: a random access memory having a plurality of addressable storage locations, each reading out its stored control data when addressed; first means for generating a clock signal having edges occurring with a period P C and for generating a beat signal having edges occurring with a period P B , wherein P C and P B differ; a delay circuit for delaying the clock signal to produce the timing signal with a delay controlled the control data read out of said RAM; and second means for iteratively addressing and adjusting the control data stored in each of said addressable storage locations such that when any one of said storage locations is addressed and reads out control data controlling said delay, edges of the beat signal thereafter substantially coincide with edges of the output signal.
Claim 7
Independent Claim
144 words
An apparatus for generating a timing signal, the apparatus comprising: a random access memory having a plurality of addressable storage locations, each reading out its stored control data when addressed; first means for generating a clock signal having edges occurring with a period P C and for generating a beat signal having edges occurring with a period P B , wherein P C and P B differ; a delay circuit for delaying the clock signal to produce the timing signal with a delay controlled the control data read out of said RAM; and second means for iteratively addressing and adjusting the control data stored in each of said addressable storage locations such that when any one of said storage locations is addressed and reads out control data controlling said delay, edges of the beat signal thereafter substantially coincide with edges of the output signal.
Claim 8
Dependent Claim
77 words
The apparatus in accordance with claim 5 wherein said second means comprises: third means for addressing each of said addressable storage locations, fourth means for performing phase comparisons of edges of said beat signal to edges of said output signal while said second means is addressing each of said addressable storage locations, and fifth means for adjusting the control data stored in each of said addressable storage locations in accordance with a result of said phase comparisons.
Claim 9
Dependent Claim
96 words
The apparatus in accordance with claim 6 wherein said fifth means adjusts the control data stored in one of said addressable storage locations to increase the delay of said delay circuit when one of said phase comparisons indicates the edge of said beat signal lags the edge of said output signal, and wherein said fifth means adjusts the control data stored in one of said addressable storage locations to decrease the delay of said delay circuit when one of said phase comparisons indicates the edge of said beat signal leads the edge of said output signal.
Claim 10
Dependent Claim
26 words
The apparatus in accordance with claim 5 wherein P B = C (N+1)/N, where N is a number of said addressable storage locations of said RAM.
Claim 11
Dependent Claim
39 words
The apparatus in accordance with claim 8 wherein said second means adjusts the control data stored in the addressed storage location so that every Nth edge of the beat signal substantially coincides with an edge of said output signal.
Claim 12
Dependent Claim
87 words
The apparatus in accordance with claim 9 wherein said second means comprises: third means for addressing said addressable storage locations; fourth means for comparing a phase of every Nth edge of the beat signal to an edge of the output signal and producing a sequence of bits, each bit indicating whether an edge of the output signal leads an edge of the beat signal; and fifth means for adjusting the control data stored in one of said addressable storage locations in response to said sequence of bits.
Claim 13
Dependent Claim
97 words
The apparatus in accordance with claim 10 wherein wherein said fifth means adjusts the control data stored in said one of said addressable storage locations to increase the delay of said delay circuit when said sequence of bits indicates the edge of said beat signal lags the edge of said output signal, and wherein said fifth means adjusts the control data stored in said one of said addressable storage locations to decrease the delay of said delay circuit when said sequence of bits indicates the edge of said beat signal leads the edge of said output signal.
Claim 14
Independent Claim
160 words
An apparatus for generating a plurality of timing signals comprising: first means for generating a clock signal having edges occurring with a period P C and a beat signal having edges occurring with a period P B , wherein P B and P C differ; and a plurality of timing signal generators, each receiving the clock and the beat signal, and each comprising: a random access memory having a plurality of addressable storage locations, each reading out its stored control data when addressed; a delay circuit for delaying the clock signal to produce the timing signal with a delay controlled the control data read out of said RAM; and second means for iteratively addressing and adjusting the control data stored in each of said addressable storage locations such that when any one of said storage locations is addressed and reads out control data controlling said delay, edges of the beat signal thereafter substantially coincide with edges of the output signal.
Claim 15
Independent Claim
160 words
An apparatus for generating a plurality of timing signals comprising: first means for generating a clock signal having edges occurring with a period P C and a beat signal having edges occurring with a period P B , wherein P B and P C differ; and a plurality of timing signal generators, each receiving the clock and the beat signal, and each comprising: a random access memory having a plurality of addressable storage locations, each reading out its stored control data when addressed; a delay circuit for delaying the clock signal to produce the timing signal with a delay controlled the control data read out of said RAM; and second means for iteratively addressing and adjusting the control data stored in each of said addressable storage locations such that when any one of said storage locations is addressed and reads out control data controlling said delay, edges of the beat signal thereafter substantially coincide with edges of the output signal.
Claim 16
Dependent Claim
77 words
The apparatus in accordance with claim 12 wherein said second means comprises: third means for addressing each of said addressable storage locations, fourth means for performing phase comparisons of edges of said beat signal to edges of said output signal while said second means is addressing each of said addressable storage locations, and fifth means for adjusting the control data stored in each of said addressable storage locations in accordance with a result of said phase comparisons.
Claim 17
Dependent Claim
96 words
The apparatus in accordance with claim 13 wherein said fifth means adjusts the control data stored in one of said addressable storage locations to increase the delay of said delay circuit when one of said phase comparisons indicates the edge of said beat signal lags the edge of said output signal, and wherein said fifth means adjusts the control data stored in one of said addressable storage locations to decrease the delay of said delay circuit when one of said phase comparisons indicates the edge of said beat signal leads the edge of said output signal.
Claim 18
Dependent Claim
26 words
The apparatus in accordance with claim 12 wherein P B = C (N+1)/N, where N is a number of said addressable storage locations of said RAM.
Claim 19
Dependent Claim
39 words
The apparatus in accordance with claim 15 wherein said second means adjusts the control data stored in the addressed storage location so that every Nth edge of the beat signal substantially coincides with an edge of said output signal.
Claim 20
Dependent Claim
87 words
The apparatus in accordance with claim 12 wherein said second means comprises: third means for addressing said addressable storage locations; fourth means for comparing a phase of every Nth edge of the beat signal to an edge of the output signal and producing a sequence of bits, each bit indicating whether an edge of the output signal leads an edge of the beat signal; and fifth means for adjusting the control data stored in one of said addressable storage locations in response to said sequence of bits.
Claim 21
Dependent Claim
97 words
The apparatus in accordance with claim 17 wherein wherein said fifth means adjusts the control data stored in said one of said addressable storage locations to increase the delay of said delay circuit when said sequence of bits indicates the edge of said beat signal lags the edge of said output signal, and wherein said fifth means adjusts the control data stored in said one of said addressable storage locations to decrease the delay of said delay circuit when said sequence of bits indicates the edge of said beat signal leads the edge of said output signal.
Claim 22
Independent Claim
179 words
An apparatus for generating an output signal in response to an input signal with a delay controlled by input data, the apparatus comprising: a delay circuit for delaying an input signal to produce said output signal with a delay controlled by control data supplied to said delay circuit, a plurality of addressable storage locations addressed by said input data for storing control data, each reading out its stored control data to said delay circuit for controlling said delay when addressed by said input data, a linearization system for automatically adjusting the value of the control data stored in each of said plurality of addressable storage locations so that the delay provided by the delay circuit is a linear function of a value of the input data, the linearization system comprising: means for generating a beat signal having edges occurring with a period P B and a clock signal having edges occurring with a period P C , where P C and P B differ, and means for applying the clock signal as said input signal to said delay circuit.
Claim 23
Independent Claim
179 words
An apparatus for generating an output signal in response to an input signal with a delay controlled by input data, the apparatus comprising: a delay circuit for delaying an input signal to produce said output signal with a delay controlled by control data supplied to said delay circuit, a plurality of addressable storage locations addressed by said input data for storing control data, each reading out its stored control data to said delay circuit for controlling said delay when addressed by said input data, a linearization system for automatically adjusting the value of the control data stored in each of said plurality of addressable storage locations so that the delay provided by the delay circuit is a linear function of a value of the input data, the linearization system comprising: means for generating a beat signal having edges occurring with a period P B and a clock signal having edges occurring with a period P C , where P C and P B differ, and means for applying the clock signal as said input signal to said delay circuit.
Claim 24
Dependent Claim
46 words
The apparatus in accordance with claim 19 further comprising: means for performing phase comparisons of edges of said beat signal to edges of said output signal; means for adjusting the control data stored in said plurality of addressable storage locations in response to said phase comparisons.
Claim 25
Dependent Claim
23 words
The apparatus in accordance with claim 19 wherein P B =P C (N+1)/N, where N is a number of said addressable storage locations.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-10 | 2005-06-11 | 2005-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-10 | 2009-06-11 | 2009-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-10 | 2013-06-11 | 2013-12-11 | $7700.00 | Window Closed / Lapsed |