US6476653B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
DLL circuit adjustable with external load
Assignee: Socionext Inc
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Filing: 1999-08-04
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Granted: 2002-11-05
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Expires: 2019-08-04
Abstract
Abstract The present invention provides a DLL circuit performing a phase adjustment in accordance to an output load, and capable of adjusting the phase in a shot time. In the present invention, in a delayed lock loop (DLL) circuit that generates a control clock having a prescribed phase relationship with a reference clock by delaying the reference clock, the operating delay time of an output buffer is measured and the timing of the control clock is adjusted in accordance with this operating delay time. As a result, the timing of the output clock of the first variable delay circuit delay circuit is adjusted in accordance with the magnitude of the external load. This output clock or the output clock of a separate variable delay circuit subject to the same delay control is then utilized as a control clock.
Inventors
- 👤 Yasurou Matsuzaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:45
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; G; G11; G11C; G11C8/00; G11C11/00; G11C11/21; G11C11/34; H03L7/0816
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
200 words
A delayed lock loop (DLL) circuit, connected to an output buffer, that generates a control clock having a prescribed phase relationship with a reference clock by delaying the reference clock, in which the output buffer supplies an output signal to an output terminal in response to the control clock, said DLL circuit comprises: a first variable delay circuit that receives said reference clock and outputs the control clock and a first delayed clock delayed from the reference clock by a controlled delay time; a second variable delay circuit that receives the first delayed clock of said first variable delay circuit and outputs a second delayed clock delayed from the first delayed clock by a prescribed delay time; a phase comparison/delay control circuit that compares the phase of said reference clock and said second delayed clock and controls the amount of delay of said first variable delay circuit such that the phase of said reference clock and of the second delayed clock are in a prescribed relationship; and a delay measurement circuit that measures an operating delay time of said output buffer and sets the delay amount of said second variable delay circuit in accordance with the measured operating delay time.
Claim 2
Dependent Claim
200 words
A delayed lock loop (DLL) circuit, connected to an output buffer, that generates a control clock having a prescribed phase relationship with a reference clock by delaying the reference clock, in which the output buffer supplies an output signal to an output terminal in response to the control clock, said DLL circuit comprises: a first variable delay circuit that receives said reference clock and outputs the control clock and a first delayed clock delayed from the reference clock by a controlled delay time; a second variable delay circuit that receives the first delayed clock of said first variable delay circuit and outputs a second delayed clock delayed from the first delayed clock by a prescribed delay time; a phase comparison/delay control circuit that compares the phase of said reference clock and said second delayed clock and controls the amount of delay of said first variable delay circuit such that the phase of said reference clock and of the second delayed clock are in a prescribed relationship; and a delay measurement circuit that measures an operating delay time of said output buffer and sets the delay amount of said second variable delay circuit in accordance with the measured operating delay time.
Claim 3
Dependent Claim
78 words
The DLL circuit of claim 1 wherein said reference clock is supplied through an input buffer and said delay measurement circuit measures a total delay period of the operating delay time of said output buffer and a delay time of a dummy input buffer having a delay time which is equivalent to a delay time of said input buffer, and sets the delay amount of said second variable delay circuit to be equivalent to said total delay time.
Claim 4
Dependent Claim
33 words
The DLL circuit of claim 1 , wherein said delay measurement circuit measures a period from a timing of said control clock to a timing of said output signal of said output buffer.
Claim 5
Dependent Claim
39 words
The DLL circuit of claim 2 or 3 wherein said delay measurement circuit operates when changeover of said output signal so as to measure a period from a timing of said control clock until changeover of said output signal.
Claim 6
Dependent Claim
24 words
The DLL circuit of claim 2 or 3 wherein said delay measurement circuit measures said period in the initialization condition on power source start-up.
Claim 7
Dependent Claim
31 words
The DLL circuit of claim 2 or 3 wherein said delay measurement circuit measures said period with a periodic timing in an ordinary condition of a device including the DLL circuit.
Claim 8
Dependent Claim
32 words
The DLL circuit of claim 5 further comprising a dummy data generating circuit that generates dummy data and wherein, in said initialization condition, said dummy data is supplied to said output buffer.
Claim 9
Dependent Claim
24 words
The DLL circuit of claim 1 wherein the first delayed clock of said first variable delay circuit is the same as said control clock.
Claim 10
Dependent Claim
67 words
The DLL circuit of claim 1 , wherein said first variable delay circuit comprises a third variable delay circuit that is supplied with said reference clock, said third variable delay circuit being controlled to a delay amount which is the same as said first variable delay circuit, and the output clock of said third variable delay circuit being supplied to said output buffer as said control clock.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-11-04 | 2006-05-06 | 2006-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-11-04 | 2010-05-06 | 2010-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-11-04 | 2014-05-06 | 2014-11-05 | $7700.00 | Window Closed / Lapsed |