US5822255A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit for supplying a control signal to a plurality of object circuits
Assignee: Socionext Inc
•
Filing: 1997-01-30
•
Granted: 1998-10-13
•
Expires: 2017-01-30
Abstract
Abstract A semiconductor integrated circuit has first and second delay controllers for receiving an input signal, a plurality of object circuits for receiving an internal signal from the first delay circuit through a real line, and a phase comparator. The phase comparator receives the input signal and a dummy internal signal from the second delay controller through a dummy line, and compares the phases of the received signals with each other. Further, the phase comparator controls delays in the first and second delay controllers according to the comparison result. The length of the real line from the first delay controller to any one of the object circuits is substantially identical, and a load value of the dummy line is substantially equal to that of the real line between the first delay controller and any one of the object circuits. Therefore, each of the object circuits or pads receives a phase-locked control signal without regard to the physical position thereof.
Inventors
- 👤 Toshiya Uchida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:36
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F1/00; G06F1/04; G06F1/10; H03K; H03K5/00; H03K5/13; H03K5/131; H03L7/081; H03L7/0812; H03L7/0816
Claims Analysis
Total Claims: 54
Claim 1
Independent Claim
142 words
A semiconductor integrated circuit having: first and second delay controllers for receiving an input signal; a plurality of object circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: a length of said real line from said first delay controller to any one of said object circuits is substantially identical; and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of said object circuits.
Claim 2
Dependent Claim
142 words
A semiconductor integrated circuit having: first and second delay controllers for receiving an input signal; a plurality of object circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: a length of said real line from said first delay controller to any one of said object circuits is substantially identical; and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of said object circuits.
Claim 3
Dependent Claim
39 words
A semiconductor integrated circuit as claimed in claim 1, wherein a length of said dummy line is substantially equal to the length of said real line between said first delay controller and the specific one of said object circuits.
Claim 4
Dependent Claim
46 words
A semiconductor integrated circuit as claimed in claim 1, wherein said real line has a tree shape between said first delay controller and said object circuits so as to determine the length of said real line to any one of said object circuits to be identical.
Claim 5
Dependent Claim
23 words
A semiconductor integrated circuit as claimed in claim 1, wherein the input signal is a clock signal for supply to said object circuits.
Claim 6
Dependent Claim
31 words
A semiconductor integrated circuit as claimed in claim 1, wherein said semiconductor integrated circuit is a synchronous DRAM, and said object circuits are data output buffer circuits of said synchronous DRAM.
Claim 7
Dependent Claim
24 words
A semiconductor-integrated circuit as claimed in claim 5, wherein the input signal is an enable signal for each of said data output buffer circuits.
Claim 8
Dependent Claim
137 words
A semiconductor integrated circuit having: first and second delay controllers for receiving an input signal; a plurality of object circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: said real line from said first delay controller to said object circuits has a symmetrical tree shape; and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and any one of said object circuits.
Claim 9
Dependent Claim
137 words
A semiconductor integrated circuit having: first and second delay controllers for receiving an input signal; a plurality of object circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: said real line from said first delay controller to said object circuits has a symmetrical tree shape; and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and any one of said object circuits.
Claim 10
Dependent Claim
38 words
A semiconductor integrated circuit as claimed in claim 7, wherein a length of said dummy line is substantially equal to a length of said real line between said first delay controller and any one of said object circuits.
Claim 11
Dependent Claim
23 words
A semiconductor integrated circuit as claimed in claim 7, wherein the input signal is a clock signal for supply to said object circuits.
Claim 12
Dependent Claim
31 words
A semiconductor integrated circuit as claimed in claim 7, wherein said semiconductor integrated circuit is a synchronous DRAM, and said object circuits are data output buffer circuits of said synchronous DRAM.
Claim 13
Dependent Claim
25 words
A semiconductor integrated circuit as claimed in claim 10, wherein the input signal is an enable signal for each of said data output buffer circuits.
Claim 14
Dependent Claim
161 words
A semiconductor integrated circuit having: first and second delay controllers for receiving an input signal; a plurality of object circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: said object circuits are arranged in groups each having a node for receiving the internal signal output from said first delay controller, said real line from said first delay controller to the nodes is laid out in a symmetrical tree shape, and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of the nodes.
Claim 15
Dependent Claim
161 words
A semiconductor integrated circuit having: first and second delay controllers for receiving an input signal; a plurality of object circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: said object circuits are arranged in groups each having a node for receiving the internal signal output from said first delay controller, said real line from said first delay controller to the nodes is laid out in a symmetrical tree shape, and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of the nodes.
Claim 16
Dependent Claim
39 words
A semiconductor integrated circuit as claimed in claim 12, wherein a length of said dummy line is substantially equal to a length of said real line between said first delay controller and the specific one of said object circuits.
Claim 17
Dependent Claim
23 words
A semiconductor integrated circuit as claimed in claim 12, wherein the input signal is a clock signal for supply to said object circuits.
Claim 18
Dependent Claim
31 words
A semiconductor integrated circuit as claimed in claim 12, wherein said semiconductor integrated circuit is a synchronous DRAM, and said object circuits are data output buffer circuits of said synchronous DRAM.
Claim 19
Dependent Claim
25 words
A semiconductor integrated circuit as claimed in claim 15, wherein the input signal is an enable signal for each of said data output buffer circuits.
Claim 20
Dependent Claim
149 words
A semiconductor integrated circuit module having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: a length of said real line from said first delay controller to any one of said object semiconductor integrated circuits is substantially identical; and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of said object semiconductor integrated circuits.
Claim 21
Dependent Claim
149 words
A semiconductor integrated circuit module having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: a length of said real line from said first delay controller to any one of said object semiconductor integrated circuits is substantially identical; and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of said object semiconductor integrated circuits.
Claim 22
Dependent Claim
42 words
A semiconductor integrated circuit module as claimed in claim 17, wherein a length of said dummy line is substantially equal to the length of said real line between said first delay controller and the specific one of said object semiconductor integrated circuits.
Claim 23
Dependent Claim
51 words
A semiconductor integrated circuit module as claimed in claim 17, wherein said real line has a tree shape between said first delay controller and said object semiconductor integrated circuits so as to determine the length of said real line to any one of said object semiconductor integrated circuits to be identical.
Claim 24
Dependent Claim
36 words
A semiconductor integrated circuit module as claimed in claim 17, wherein said semiconductor integrated circuit module is a memory module, and each of said object semiconductor integrated circuits is a memory chip of said memory module.
Claim 25
Dependent Claim
35 words
A semiconductor integrated circuit module as claimed in claim 17, wherein the input signal is a clock signal, and an input terminal of each of said object semiconductor integrated circuits is a clock input terminal.
Claim 26
Dependent Claim
144 words
A semiconductor integrated circuit module having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: said real line from said first delay controller to said object semiconductor integrated circuits has a symmetrical tree shape; and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and any one of said object semiconductor integrated circuits.
Claim 27
Dependent Claim
144 words
A semiconductor integrated circuit module having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: said real line from said first delay controller to said object semiconductor integrated circuits has a symmetrical tree shape; and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and any one of said object semiconductor integrated circuits.
Claim 28
Dependent Claim
41 words
A semiconductor integrated circuit module as claimed in claim 22, wherein a length of said dummy line is substantially equal to a length of said real line between said first delay controller and any one of said object semiconductor integrated circuits.
Claim 29
Dependent Claim
36 words
A semiconductor integrated circuit module as claimed in claim 22, wherein said semiconductor integrated circuit module is a memory module, and each of said object semiconductor integrated circuits is a memory chip of said memory module.
Claim 30
Dependent Claim
35 words
A semiconductor integrated circuit module as claimed in claim 22, wherein the input signal is a clock signal, and an input terminal of each of said object semiconductor integrated circuits is a clock input terminal.
Claim 31
Dependent Claim
166 words
A semiconductor integrated circuit module having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: said object semiconductor integrated circuits are arranged in groups each having a node for receiving the internal signal output from said first delay controller, said real line from said first delay controller to the nodes is laid out in a symmetrical tree shape, and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of the nodes.
Claim 32
Dependent Claim
166 words
A semiconductor integrated circuit module having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: said object semiconductor integrated circuits are arranged in groups each having a node for receiving the internal signal output from said first delay controller, said real line from said first delay controller to the nodes is laid out in a symmetrical tree shape, and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of the nodes.
Claim 33
Dependent Claim
42 words
A semiconductor integrated circuit module as claimed in claim 26, wherein a length of said dummy line is substantially equal to a length of said real line between said first delay controller and the specific one of said object semiconductor integrated circuits.
Claim 34
Dependent Claim
36 words
A semiconductor integrated circuit module as claimed in claim 26, wherein said semiconductor integrated circuit module is a memory module, and each of said object semiconductor integrated circuits is a memory chip of said memory module.
Claim 35
Dependent Claim
35 words
A semiconductor integrated circuit module as claimed in claim 26, wherein the input signal is a clock signal, and an input terminal of each of said object semiconductor integrated circuits is a clock input terminal.
Claim 36
Dependent Claim
152 words
A semiconductor integrated circuit system having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuit modules for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: a length of said real line from said first delay controller to any one of said object semiconductor integrated circuit modules is substantially identical; and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of said object semiconductor integrated circuit modules.
Claim 37
Dependent Claim
152 words
A semiconductor integrated circuit system having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuit modules for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: a length of said real line from said first delay controller to any one of said object semiconductor integrated circuit modules is substantially identical; and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of said object semiconductor integrated circuit modules.
Claim 38
Dependent Claim
43 words
A semiconductor integrated circuit system as claimed in claim 30, wherein a length of said dummy line is substantially equal to the length of said real line between said first delay controller and the specific one of said object semiconductor integrated circuit modules.
Claim 39
Dependent Claim
53 words
A semiconductor integrated circuit system as claimed in claim 30, wherein said real line has a tree shape between said first delay controller and said object semiconductor integrated circuit modules so as to determine the length of said real line to any one of said object semiconductor integrated circuit modules to be identical.
Claim 40
Dependent Claim
41 words
A semiconductor integrated circuit system as claimed in claim 30, wherein each of said object semiconductor integrated circuit modules is a memory module, and an input terminal of each of said object semiconductor integrated circuit modules is a clock input terminal.
Claim 41
Dependent Claim
147 words
A semiconductor integrated circuit system having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuit modules for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: said real line from said first delay controller to said object semiconductor integrated circuit modules has a symmetrical tree shape; and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and any one of said object semiconductor integrated circuit modules.
Claim 42
Dependent Claim
147 words
A semiconductor integrated circuit system having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuit modules for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: said real line from said first delay controller to said object semiconductor integrated circuit modules has a symmetrical tree shape; and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and any one of said object semiconductor integrated circuit modules.
Claim 43
Dependent Claim
42 words
A semiconductor integrated circuit system as claimed in claim 34, wherein a length of said dummy line is substantially equal to a length of said real line between said first delay controller and any one of said object semiconductor integrated circuit modules.
Claim 44
Dependent Claim
41 words
A semiconductor integrated circuit system as claimed in claim 34, wherein each of said object semiconductor integrated circuit modules is a memory module, and an input terminal of each of said object semiconductor integrated circuit modules is a clock input terminal.
Claim 45
Dependent Claim
168 words
A semiconductor integrated circuit system having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuit modules for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: said object semiconductor integrated circuit modules are arranged in groups each having a node for receiving the internal signal output from said first delay controller, said real line from said first delay controller to the nodes is laid out in a symmetrical tree shape, and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of the nodes.
Claim 46
Dependent Claim
168 words
A semiconductor integrated circuit system having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuit modules for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: said object semiconductor integrated circuit modules are arranged in groups each having a node for receiving the internal signal output from said first delay controller, said real line from said first delay controller to the nodes is laid out in a symmetrical tree shape, and a load value of said dummy line is substantially equal to that of said real line between said first delay controller and a specific one of the nodes.
Claim 47
Dependent Claim
43 words
A semiconductor integrated circuit system as claimed in claim 37, wherein a length of said dummy line is substantially equal to a length of said real line between said first delay controller and the specific one of said object semiconductor integrated circuit modules.
Claim 48
Dependent Claim
41 words
A semiconductor integrated circuit system as claimed in claim 37, wherein each of said object semiconductor integrated circuit modules is a memory module, and an input terminal of each of said object semiconductor integrated circuit modules is a clock input terminal.
Claim 49
Dependent Claim
122 words
A semiconductor integrated circuit having: first and second delay controllers for receiving an input signal; a plurality of object circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: a load value of said dummy line is substantially equal to that of an average length of said real lines from said first delay controller to said plurality of object circuits.
Claim 50
Dependent Claim
122 words
A semiconductor integrated circuit having: first and second delay controllers for receiving an input signal; a plurality of object circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: a load value of said dummy line is substantially equal to that of an average length of said real lines from said first delay controller to said plurality of object circuits.
Claim 51
Dependent Claim
127 words
A semiconductor integrated circuit module having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: a load value of said dummy line is substantially equal to that of an average length of said real lines from said first delay controller to said plurality of object semiconductor integrated circuits.
Claim 52
Dependent Claim
127 words
A semiconductor integrated circuit module having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuits for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: a load value of said dummy line is substantially equal to that of an average length of said real lines from said first delay controller to said plurality of object semiconductor integrated circuits.
Claim 53
Dependent Claim
129 words
A semiconductor integrated circuit system having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuit modules for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: a load value of said dummy line is substantially equal to that of an average length of said real lines from said first delay controller to said plurality of object semiconductor integrated circuit modules.
Claim 54
Dependent Claim
129 words
A semiconductor integrated circuit system having: first and second delay controllers for receiving an input signal; a plurality of object semiconductor integrated circuit modules for receiving an internal signal output from said first delay circuit through a real line; and a phase comparator for receiving the input signal and a dummy internal signal output from said second delay controller through a dummy line, for comparing phases of the received input and dummy internal signals with each other, and for controlling delays in said first and second delay controllers in accordance with the comparison result, wherein: a load value of said dummy line is substantially equal to that of an average length of said real lines from said first delay controller to said plurality of object semiconductor integrated circuit modules.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |