Variable delay circuit and method, and delay locked loop, memory device and computer system using same

Claim 2

A variable delay circuit for delaying an input clock signal applied to a clock input terminal to produce a delayed clock signal at a clock output terminal, the variable delay circuit comprising: a plurality of inverting logic circuits arranged in series with each other; a delay select circuit receiving at least one delay command signal indicative of a delay of the variable delay circuit, the delay select circuit being operable to generate at least one control signal responsive to the delay command signal, the delay circuit comprising a shift register having a plurality of stages each of which provides a respective control signal, one of the shift register stages storing a unique data bit that is different from the data bits stored in the other shift register stages; and a clock transfer control circuit coupled to the inverting logic circuits, the delay select circuit, and the clock input terminal, the clock transfer control circuit being operable responsive to the at least one control signal to vary the number of inverting logic circuits through which the input clock signal is coupled between the clock input terminal and the clock output terminal, the clock transfer control circuit further being operable to adjust the polarity of the input clock signal between the clock input terminal and the clock output terminal as a function of the at least one control signal, the clock transfer control circuit comprising: a plurality of pass gates each of which is coupled between the output of a respective inverting logic circuit and the output terminal, each of the pass gates having a control terminal coupled to a respective stage of the shift register; and a polarity control circuit coupled to the inverting logic circuits so that the input clock signal is coupled through the polarity control circuit between the input terminal and the output terminal, the polarity control circuit being operable to alternately invert and not invert the clock signal coupled therethrough as the unique data bit shifts from one shift register stage to the next.

Claim 3

The variable delay circuit of claim 1 wherein the clock transfer control circuit is operable responsive to the at least one control signal to select the entry point of the input clock signal into the plurality of inverting logic circuits.

Claim 4

The variable delay circuit of claim 1 wherein the clock transfer control circuit is operable responsive to the at least one control signal to select an exit point of the delayed clock signal from the plurality of inverting logic circuits.

Claim 5

The variable delay circuit of claim 1 wherein each of the inverting logic circuits comprise an inverter.

Claim 6

The variable delay circuit of claim 1 wherein each of the inverting logic circuits comprise a logic gate.

Claim 7

The variable delay circuit of claim 1 wherein the polarity control circuit is coupled between the clock input terminal and a first in the series of the inverting logic circuits.

Claim 8

The variable delay circuit of claim 1 wherein the polarity control circuit comprises: an exclusive logic gate having at least first and second inputs, the first input being coupled to receive the input clock signal; and a toggle circuit having an output that is coupled to the second input of the exclusive logic gate, the toggle circuit being operable to change a logic level on the output of the toggle circuit between two values responsive to shifting of the unique data bit from one shift register stage to the next.

Claim 9

The variable delay circuit of claim 7 wherein the exclusive logic gate comprises an exclusive NOR-gate.

Claim 10

The variable delay circuit of claim 7 wherein, the toggle circuit comprises a flip-flop having a data input, a clock input, and an output, the output being coupled to the second input of the exclusive logic gate and to the data input of the flip-flop in inverting fashion so that clocking the output of the flip-flop that is coupled to the data input of the flip-flop cause a change in the flip-flop output, the flip-flop being clocked responsive to changes in the at least one command signal indicative of changes in the delay of the variable delay circuit.

Claim 11

The variable delay circuit of claim 1 wherein the polarity control circuit comprises: an inverter coupled to receive the input clock signal, the inverter generating a complimentary clock signal; a first pass gate coupling the input clock signal to a first in the series of inverting logic circuits; a second pass gate coupling the complimentary clock signal to the first in the series of inverting logic circuits; and a toggle circuit having an output and being operable to change a logic level on the output of the toggle circuit between two values responsive to shifting of the unique data bit from one shift register stage to the next, the output of the toggle circuit being coupled to respective control inputs of both of the pass gates, the control input of one of the pass gates being coupled to the toggle circuit through an inverter so that the first and second pass gates are alternately enabled and disabled.

Claim 12

The variable delay circuit of claim 10 wherein the toggle circuit comprises a flip-flop having a data input, a clock, input, and an output, the output being coupled to the control inputs of the pass gates and to the data input of the flip-flop in inverting fashion so that clocking the output of the flip-flop that is coupled to the data input of the flip-flop cause a change in the flip-flop output, the flip-flop being clocked responsive to changes in the at least one command signal indicative of changes in the delay of the variable delay circuit.

Claim 13

The variable delay circuit of claim 1 wherein the inverting logic circuits comprise a plurality of inverting logic gates coupled together in a series, the inverting logic gates having respective first inputs, and wherein the clock transfer control circuit comprises: an inverter coupled to receive the input clock signal, the inverter generating a complimentary clock signal; and a plurality of control logic gates each having a first input coupled to a respective stage of the shift register and an output coupled to the first input of a respective inverting logic gate, the second inputs of alternating control logic gates being coupled to receive the input clock signal, and the second inputs of the remaining control logic gates being coupled to receive the complimentary clock signal.

Claim 14

The variable delay circuit of claim 12 wherein the inverting logic circuits comprise alternating delaying NOR-gates and delaying NAND-gates coupled in series with each other, and wherein the control logic gates comprise alternating control NOR-gates and control NAND-gates with the delaying NOR-gates receiving an output from a respective control NOR-gate and the delaying NAND-gates receiving an output from a control NAND-gate.

Claim 15

A variable delay circuit for delaying an input clock signal applied to a clock input terminal to produce a delayed clock signal at a clock output terminal, the variable delay circuit comprising: a plurality of inverters arranged in series with each other; a shift register having a plurality of stages each of which provides-a respective output signal, one of the shift register stages storing a unique data bit that is different from the data bits stored in the other shift register stages, the shift register being operable to shift the unique data bit in one direction responsive to a delay increase signal, and to shift the unique data bit in an opposite direction responsive to a delay decrease signal; a plurality of pass gates each of which is coupled between the output of a respective inverter and the output terminal, each of the pass gates having a control terminal coupled to the output of a respective stage of the shift register; and a polarity control circuit coupled between the clock input terminal and a first in the series of the inverters, the polarity control circuit being operable to alternately invert and not invert the clock signal coupled therethrough responsive to each delay increase signal and each delay decrease signal.

Claim 16

A variable delay circuit for delaying an input clock signal applied to a clock input terminal to produce a delayed clock signal at a clock output terminal, the variable delay circuit comprising: a plurality of inverters arranged in series with each other; a shift register having a plurality of stages each of which provides-a respective output signal, one of the shift register stages storing a unique data bit that is different from the data bits stored in the other shift register stages, the shift register being operable to shift the unique data bit in one direction responsive to a delay increase signal, and to shift the unique data bit in an opposite direction responsive to a delay decrease signal; a plurality of pass gates each of which is coupled between the output of a respective inverter and the output terminal, each of the pass gates having a control terminal coupled to the output of a respective stage of the shift register; and a polarity control circuit coupled between the clock input terminal and a first in the series of the inverters, the polarity control circuit being operable to alternately invert and not invert the clock signal coupled therethrough responsive to each delay increase signal and each delay decrease signal.

Claim 17

The variable delay circuit of claim 14 wherein the polarity control circuit comprises: an exclusive logic gate having at least first and second inputs, the first input being coupled to receive the input clock signal; and a toggle circuit having an output that is coupled to the second input of the exclusive logic gate, the toggle circuit being operable to change a logic level on the output of the toggle circuit between two values responsive to each delay increase signal and each delay decrease signal.

Claim 18

The variable delay circuit of claim 15 wherein the exclusive logic gate comprises an exclusive NOR-gate.

Claim 19

The variable delay circuit of claim 15 wherein the toggle circuit comprises a flip-flop having a data input, a clock input, and an output, the output being coupled to the second input of the exclusive logic gate and to the data input of the flip-flop in inverting fashion so that clocking the output of the flip-flop that is coupled to the data input of the flip-flop cause a change in the flip-flop output, the flip-flop being clocked responsive to each delay increase signal and each delay decrease signal.

Claim 20

The variable delay circuit of claim 14 wherein the polarity control circuit comprises: an inverter coupled to receive the input clock signal, the inverter generating a complimentary clock signal; a first pass gate coupling the input clock signal to a first in the series of inverters; a second pass gate coupling the complimentary clock signal to the first in the series of inverters; and a toggle circuit having an output and being operable to change a logic level on the output of the toggle circuit between two values responsive to each delay increase signal and each delay decrease signal, the output of the toggle circuit being coupled to respective control inputs of both of the pass gates, the control input of one of the pass gates being coupled to the toggle circuit through an inverter so that the first and second pass gates are alternately enabled and disabled.

Claim 21

The variable delay circuit of claim 18 wherein the toggle circuit comprises a flip-flop having a data input, a clock input, and an output, the output being coupled to the control inputs of the pass gates and to the data input of the flip-flop in inverting fashion so that clocking the output of the flip-flop that is coupled to the data input of the flip-flop cause a change in the flip-flop output, the flip-flop being clocked responsive to each delay increase signal and each delay decrease signal.

Claim 22

A variable delay circuit for delaying an input clock signal applied to a clock input terminal to produce a delayed clock signal at a clock output terminal, the variable delay circuit comprising: a plurality of inverting logic circuits arranged in series with each other, each of the inverting logic circuits comprising a plurality of inverting logic gates coupled together in a series, the inverting logic gates having respective first inputs; a delay select circuit receiving at least one delay command signal indicative of a delay of the variable delay circuit, the delay select circuit being operable to generate at least one control signal responsive to the delay command signal, the delay select circuit comprising a shift register having a plurality of stages each of which provides a respective control signal, one of the shift register stages storing a unique data bit that is different from the data bits stored in the other shift register stages; and a clock transfer control circuit coupled to the inverting logic circuits, the delay select circuit, and the clock input terminal, the clock transfer control circuit being operable responsive to the at least one control signal to vary the number of inverting logic circuits through which the input clock signal is coupled between the clock input terminal and the clock output terminal, the clock transfer control circuit further being operable to adjust the polarity of the input clock signal between the clock input terminal and the clock output terminal as a function of the at least one control signal, the clock transfer control circuit comprising: an inverter coupled to receive the input clock signal, the inverter generating a complimentary clock signal; and a plurality of control logic gates each having a first input coupled to a respective stage of the shift register and an output coupled to the first input of a respective inverting logic gate, the second inputs of alternating control logic gates being coupled to receive the input clock signal, and the second inputs of the remaining control logic gates being coupled to receive the complimentary clock signal.

Claim 23

A variable delay circuit for delaying an input clock signal applied to a clock input terminal to produce a delayed clock signal at a clock output terminal, the variable delay circuit comprising: a plurality of inverting logic circuits arranged in series with each other, each of the inverting logic circuits comprising a plurality of inverting logic gates coupled together in a series, the inverting logic gates having respective first inputs; a delay select circuit receiving at least one delay command signal indicative of a delay of the variable delay circuit, the delay select circuit being operable to generate at least one control signal responsive to the delay command signal, the delay select circuit comprising a shift register having a plurality of stages each of which provides a respective control signal, one of the shift register stages storing a unique data bit that is different from the data bits stored in the other shift register stages; and a clock transfer control circuit coupled to the inverting logic circuits, the delay select circuit, and the clock input terminal, the clock transfer control circuit being operable responsive to the at least one control signal to vary the number of inverting logic circuits through which the input clock signal is coupled between the clock input terminal and the clock output terminal, the clock transfer control circuit further being operable to adjust the polarity of the input clock signal between the clock input terminal and the clock output terminal as a function of the at least one control signal, the clock transfer control circuit comprising: an inverter coupled to receive the input clock signal, the inverter generating a complimentary clock signal; and a plurality of control logic gates each having a first input coupled to a respective stage of the shift register and an output coupled to the first input of a respective inverting logic gate, the second inputs of alternating control logic gates being coupled to receive the input clock signal, and the second inputs of the remaining control logic gates being coupled to receive the complimentary clock signal.

Claim 24

The variable delay circuit of claim 20 wherein the clock transfer control circuit is operable responsive to the at least one control signal to select the entry point of the input clock signal into the plurality of inverting logic circuits.

Claim 25

The variable delay circuit of claim 20 wherein the clock transfer control circuit is operable responsive to the at least one control signal to select an exit point of the delayed clock signal from the plurality of inverting logic circuits.

Claim 26

The variable delay circuit of claim 20 wherein each of the inverting logic circuits comprise an inverter.

Claim 27

The variable delay circuit of claim 20 wherein each of the inverting logic circuits comprise a logic gate.

Claim 28

The variable delay circuit of claim 20 wherein the inverting logic circuits comprise alternating delaying NOR-gates and delaying NAND-gates coupled in series with each other, and wherein the control logic gates comprise alternating control NOR-gates and control NAND-gates with the delaying NOR-gates receiving an output from a respective control NOR-gate and the delaying NAND-gates receiving an output from a control NAND-gate.