Method and apparatus for digital delay locked loop circuits

Claim 2

A processor system comprising: a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop circuit for synchronizing the required clock signals for said integrated circuits, said digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after said input signal; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a first phase detect signal and a second phase detect signal related to the difference in phase between said input and delayed output signals; a shift register connected to said phase detect circuit for controlling a delay of said delay line proportional to said first and second phase detect signals; and control circuitry coupled to said first and said second phase detect signals to provide a precharge signal to said delay line, wherein said delay line comprises at least one delay stage, each of said delay stages comprising: a first logic circuit coupled to a stage input signal; a second logic circuit coupled to a second stage input signal, wherein said second logic circuit is a NAND gate; and a switch coupled between said stage input signal and said second logic circuit, whereby a control signal will cause said switch to open or close to determine a path of said input signal, thereby controlling said predetermined time after said input signal.

Claim 3

The processor system according to claim 1 , wherein said second stage input signal for a first of said at least one delay stages is said precharge signal.

Claim 4

The processor system according to claim 2 , wherein said second stage input signal for a delay stage other than said first delay stage is an output from a preceding delay stage.

Claim 5

The processor system according to claim 1 , wherein said first logic circuit is an inverter.

Claim 6

The processor system according to claim 1 , wherein a unit delay time for each of said at least one delay stage is approximately 50 picoseconds.

Claim 7

The processor system according to claim 1 , wherein said control signal is provided by the shift register.

Claim 8

A processor system comprising: a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop circuit for synchronizing the required clock signals for said integrated circuits, said digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after said input signal, wherein said delay line comprises at least one delay stage, each of said delay stages comprising: a first logic circuit coupled to a stage input signal; a second logic circuit coupled to a second stage input signal, wherein said second stage input signal for a first of said at least one delay stages is a precharge signal; and a switch coupled between said stage input signal and said second logic circuit, whereby a control signal will cause said switch to open or close to determine a path of said input signal, thereby controlling said predetermined time after said input signal; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a first phase detect signal and a second phase detect signal related to the difference in phase between said input and delayed output signals; a shift register connected to said phase detect circuit for controlling a delay of said delay line proportional to said first and second phase detect signals; and a control circuitry comprising a third logic circuit coupled to said first and said second phase detect signals; and a fourth logic circuit coupled to an output of said third logic circuit and said delay line, whereby said fourth logic circuit toggles said precharge signal between a first logic level and a second logic level according to said first and said second phase detect signals, said control circuitry coupled to said first and said second phase detect signals to provide said precharge signal to said delay line.

Claim 9

A processor system comprising: a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop circuit for synchronizing the required clock signals for said integrated circuits, said digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after said input signal, wherein said delay line comprises at least one delay stage, each of said delay stages comprising: a first logic circuit coupled to a stage input signal; a second logic circuit coupled to a second stage input signal, wherein said second stage input signal for a first of said at least one delay stages is a precharge signal; and a switch coupled between said stage input signal and said second logic circuit, whereby a control signal will cause said switch to open or close to determine a path of said input signal, thereby controlling said predetermined time after said input signal; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a first phase detect signal and a second phase detect signal related to the difference in phase between said input and delayed output signals; a shift register connected to said phase detect circuit for controlling a delay of said delay line proportional to said first and second phase detect signals; and a control circuitry comprising a third logic circuit coupled to said first and said second phase detect signals; and a fourth logic circuit coupled to an output of said third logic circuit and said delay line, whereby said fourth logic circuit toggles said precharge signal between a first logic level and a second logic level according to said first and said second phase detect signals, said control circuitry coupled to said first and said second phase detect signals to provide said precharge signal to said delay line.

Claim 10

The processor system according to claim 7 , wherein said fourth logic circuit is a flip-flop.

Claim 11

The processor system according to claim 7 , wherein said third logic circuit is an OR gate.

Claim 12

The processor system according to claim 7 , wherein said third logic circuit is an exclusive OR gate.

Claim 13

A processor system comprising: a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop circuit for synchronizing the required clock signals for said integrated circuits, said digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after said input signal; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a first phase detect signal and a second phase detect signal related to the difference in phase between said input and delayed output signals; a shift register connected to said phase detect circuit for controlling a delay of said delay line proportional to said first and second phase detect signals; and control circuitry coupled to said first and said second phase detect signals to provide a precharge signal to said delay line, wherein said delay line comprises at least one delay stage, each of said delay stages comprising: a first logic circuit coupled to a stage input signal; a second logic circuit coupled to a second stage input signal; and a switch coupled between said stage input signal and said second logic circuit, wherein said switch is a NAND gate; whereby a control signal will cause said switch to open or close to determine a path of said input signal, thereby controlling said predetermined time after said input signal.

Claim 14

A processor system comprising: a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop circuit for synchronizing the required clock signals for said integrated circuits, said digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after said input signal; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a first phase detect signal and a second phase detect signal related to the difference in phase between said input and delayed output signals; a shift register connected to said phase detect circuit for controlling a delay of said delay line proportional to said first and second phase detect signals; and control circuitry coupled to said first and said second phase detect signals to provide a precharge signal to said delay line, wherein said delay line comprises at least one delay stage, each of said delay stages comprising: a first logic circuit coupled to a stage input signal; a second logic circuit coupled to a second stage input signal; and a switch coupled between said stage input signal and said second logic circuit, wherein said switch is a NAND gate; whereby a control signal will cause said switch to open or close to determine a path of said input signal, thereby controlling said predetermined time after said input signal.

Claim 15

A printed circuit board comprising: a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop circuit for synchronizing the required clock signals for said integrated circuits, said digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after said input signal; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a first phase detect signal and a second phase detect signal related to the difference in phase between said input and delayed output signals; a shift register connected to said phase detect circuit for controlling a delay of said delay line proportional to said first and second phase detect signals; and control circuitry coupled to said first and said second phase detect signals to provide a precharge signal to said delay line, wherein said delay line comprises at least one delay stage, each of said delay stages comprising: a first logic circuit coupled to a stage input signal; a second logic circuit coupled to a second stage input signal, wherein said second logic circuit is a NAND gate; and a switch coupled between said stage input signal and said second logic circuit, whereby a control signal will cause said switch to open or close to determine a path of said input signal, thereby controlling said predetermined time after said input signal.

Claim 16

A printed circuit board comprising: a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop circuit for synchronizing the required clock signals for said integrated circuits, said digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after said input signal; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a first phase detect signal and a second phase detect signal related to the difference in phase between said input and delayed output signals; a shift register connected to said phase detect circuit for controlling a delay of said delay line proportional to said first and second phase detect signals; and control circuitry coupled to said first and said second phase detect signals to provide a precharge signal to said delay line, wherein said delay line comprises at least one delay stage, each of said delay stages comprising: a first logic circuit coupled to a stage input signal; a second logic circuit coupled to a second stage input signal, wherein said second logic circuit is a NAND gate; and a switch coupled between said stage input signal and said second logic circuit, whereby a control signal will cause said switch to open or close to determine a path of said input signal, thereby controlling said predetermined time after said input signal.

Claim 17

The printed circuit board according to claim 12 , wherein said second stage input signal for a first of said at least one delay stages is said precharge signal.

Claim 18

The printed circuit board according to claim 13 , wherein said second stage input signal for a delay stage other than said first delay stage is an output from a preceding delay stage.

Claim 19

The printed circuit according to claim 12 , wherein said first logic circuit is an inverter.

Claim 20

The printed circuit board according to claim 12 , wherein a unit delay time for each of said at least one delay stage is approximately 50 picoseconds.

Claim 21

The printed circuit board according to claim 12 , wherein said control signal is provided by the shift register.

Claim 22

A printed circuit board comprising: a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop circuit for synchronizing the required clock signals for said integrated circuits, said digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after said input signal, wherein said delay line comprises at least one delay stage, each of said delay stages comprising: a first logic circuit coupled to a stage input signal; a second logic circuit coupled to a second stage input signal, wherein said second stage input signal for a first of said at least one delay stages is a precharge signal; and a switch coupled between said stage input signal and said second logic circuit, whereby a control signal will cause said switch to open or close to determine a path of said input signal, thereby controlling said predetermined time after said input signal; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a first phase detect signal and a second phase detect signal related to the difference in phase between said input and delayed output signals; a shift register connected to said phase detect circuit for controlling a delay of said delay line proportional to said first and second phase detect signals; and a control circuitry comprising a third logic circuit coupled to said first and said second phase detect signals; and a fourth logic circuit coupled to an output of said third logic circuit and said delay line, whereby said fourth logic circuit toggles said precharge signal between a first logic level arid a second logic level according to said first and said second phase detect signals, said control circuitry coupled to said first and said second phase detect signals to provide said precharge signal to said delay line.

Claim 23

A printed circuit board comprising: a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop circuit for synchronizing the required clock signals for said integrated circuits, said digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after said input signal, wherein said delay line comprises at least one delay stage, each of said delay stages comprising: a first logic circuit coupled to a stage input signal; a second logic circuit coupled to a second stage input signal, wherein said second stage input signal for a first of said at least one delay stages is a precharge signal; and a switch coupled between said stage input signal and said second logic circuit, whereby a control signal will cause said switch to open or close to determine a path of said input signal, thereby controlling said predetermined time after said input signal; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a first phase detect signal and a second phase detect signal related to the difference in phase between said input and delayed output signals; a shift register connected to said phase detect circuit for controlling a delay of said delay line proportional to said first and second phase detect signals; and a control circuitry comprising a third logic circuit coupled to said first and said second phase detect signals; and a fourth logic circuit coupled to an output of said third logic circuit and said delay line, whereby said fourth logic circuit toggles said precharge signal between a first logic level arid a second logic level according to said first and said second phase detect signals, said control circuitry coupled to said first and said second phase detect signals to provide said precharge signal to said delay line.

Claim 24

The printed circuit board according to claim 18 , wherein said fourth logic circuit is a flip-flop.

Claim 25

The printed circuit board according to claim 18 , wherein said third logic circuit is an OR gate.

Claim 26

The printed circuit board according to claim 18 , wherein said third logic circuit is an exclusive OR gate.

Claim 27

A printed circuit board comprising: a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop circuit for synchronizing the required clock signals for said integrated circuits, said digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after said input signal; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a first phase detect signal and a second phase detect signal related to the difference in phase between said input and delayed output signals; a shift register connected to said phase detect circuit for controlling a delay of said delay line proportional to said first and second phase detect signals; and control circuitry coupled to said first and said second phase detect signals to provide a precharge signal to said delay line, wherein said delay line comprises at least one delay stage, each of said delay stages comprising: a first logic circuit coupled to a stage input signal; a second logic circuit coupled to a second stage input signal; and a switch coupled between said stage input signal and said second logic circuit, wherein said switch is a NAND gate; whereby a control signal will cause said switch to open or close to determine a path of said input signal, thereby controlling said predetermined time after said input signal.

Claim 28

A printed circuit board comprising: a plurality of integrated circuits at least one of which is a microprocessor, each of said integrated circuits requiring a clock signal; and at least one digital delay locked loop circuit for synchronizing the required clock signals for said integrated circuits, said digital delay locked loop circuit comprising: a delay line for receiving an input signal and providing a delayed output signal a predetermined time after said input signal; a phase detect circuit for comparing the phases of the delayed output signal and the input signal and generating a first phase detect signal and a second phase detect signal related to the difference in phase between said input and delayed output signals; a shift register connected to said phase detect circuit for controlling a delay of said delay line proportional to said first and second phase detect signals; and control circuitry coupled to said first and said second phase detect signals to provide a precharge signal to said delay line, wherein said delay line comprises at least one delay stage, each of said delay stages comprising: a first logic circuit coupled to a stage input signal; a second logic circuit coupled to a second stage input signal; and a switch coupled between said stage input signal and said second logic circuit, wherein said switch is a NAND gate; whereby a control signal will cause said switch to open or close to determine a path of said input signal, thereby controlling said predetermined time after said input signal.