Semiconductor device enable to output a counter value of an internal clock generation in a test mode

Claim 2

A semiconductor device operating in synchronization with an external clock signal, comprising: a variable delay circuit delaying said external clock signal to generate an internal clock signal, capable of controlling a delay time; a phase comparator comparing phases of said external clock signal and said internal clock signal to output a first control signal to reduce the delay time of said variable delay circuit when the phase of said internal clock signal is lagging behind the phase of said external clock signal, and to output a second control signal to increase the delay time of said variable delay circuit when the phase of said internal clock signal is leading the phase of said external clock signal; an up/down counter having a count value incremented in response to one of said first and second control signals being output, and decremented in response to the other of said first and second control signals being output; an internal circuit carrying out a predetermined operation in synchronization with said internal clock signal; and an output circuit providing a signal generated by said internal circuit outside in a normal operation, and providing the count value of said up/down counter outside when in a test operation.

Claim 3

The semiconductor device according to claim 1 , wherein said up/down counter controls the delay time of said variable delay circuit according to its count value.

Claim 4

The semiconductor device according to claim 1 , further comprising a shift register including a plurality of registers connected in series, each register holding and providing a signal of a first or second logic, and shifting the output logic to a succeeding stage in response to one of said first and second control signals being output and to a preceding stage in response to the other of said first and second control signals being output, said shift register controlling the delay time of said variable delay circuit by output signals of said plurality of registers.

Claim 5

The semiconductor device according to claim 3 , wherein each of a plurality of registers of a first stage side out of the plurality of registers of said shift register holds said signal of the first logic, and each of the other registers holds said signal of the second logic.

Claim 6

The semiconductor device according to claim 3 , wherein any one of the plurality of registers of said shift register holds said signal of the first logic, and each of the other registers holds said signal of the second logic.

Claim 7

The semiconductor device according to claim 1 , wherein said internal circuit includes a memory circuit from which stored data is read out in synchronization with said internal clock signal, wherein said output circuit comprises a switch circuit receiving read out data of said memory circuit and the count value of said up/down counter to pass the read out data of said memory circuit in said normal operation and to pass the count value of said up/down counter in said test operation, and a data output circuit providing the read out data of said memory circuit and the count value of said up/down counter passing said switch circuit outside.

Claim 8

A semiconductor device operating in synchronization with an external clock signal, comprising: a variable delay circuit delaying said external clock signal to generate an internal clock signal, capable of controlling a delay time; a phase comparator comparing phases of said external clock signal and said internal clock signal to output a first control signal to reduce the delay time of said variable delay circuit in response to the phase of said internal clock signal lagging behind the phase of said external clock signal and to output a second control signal to increase the delay time of said variable delay circuit in response to the phase of said internal clock signal leading ahead the phase of said external clock signal; a shift register including a plurality of registers connected in series and divided in advance into a plurality of groups, each register holding and providing a signal of a first or second logic to shift the logic output to a succeeding stage in response to one of said first and second control signals being output and to a preceding stage in response to the other of said first and second control signals being output, said shift register controlling the delay time of said variable delay circuit according to output signals of said plurality of registers; an internal circuit carrying out a predetermined operation in synchronization with said internal clock signal; and an output circuit providing a signal generated by said internal circuit outside in a normal operation, and providing the output signal of at least one register out of each group outside in a test operation.

Claim 9

A semiconductor device operating in synchronization with an external clock signal, comprising: a variable delay circuit delaying said external clock signal to generate an internal clock signal, capable of controlling a delay time; a phase comparator comparing phases of said external clock signal and said internal clock signal to output a first control signal to reduce the delay time of said variable delay circuit in response to the phase of said internal clock signal lagging behind the phase of said external clock signal and to output a second control signal to increase the delay time of said variable delay circuit in response to the phase of said internal clock signal leading ahead the phase of said external clock signal; a shift register including a plurality of registers connected in series and divided in advance into a plurality of groups, each register holding and providing a signal of a first or second logic to shift the logic output to a succeeding stage in response to one of said first and second control signals being output and to a preceding stage in response to the other of said first and second control signals being output, said shift register controlling the delay time of said variable delay circuit according to output signals of said plurality of registers; an internal circuit carrying out a predetermined operation in synchronization with said internal clock signal; and an output circuit providing a signal generated by said internal circuit outside in a normal operation, and providing the output signal of at least one register out of each group outside in a test operation.

Claim 10

The semiconductor device according to claim 7 , wherein said output circuit provides output signals of said plurality of registers divided for output over a plurality of times in a time-divisional manner in said test operation.

Claim 11

The semiconductor device according to claim 7 , wherein any register of each group is preselected, and wherein said output circuit provides an output signal of the preselected register of each group outside in said test operation.

Claim 12

The semiconductor device according to claim 9 , wherein said output circuit provides output signals of preselected plurality of registers from said plurality of groups divided for output over a plurality of times in a time-divisional manner.

Claim 13

The semiconductor device according to claim 7 , further comprising a first logic circuit provided corresponding to each group to generate an OR, AND, or exclusive-OR signal of output signals of a plurality of registers belonging to a corresponding group, wherein said output circuit provides an output signal of each first logic circuit outside in said test operation.

Claim 14

The semiconductor device according to claim 11 , wherein said output circuit provides output signals of a plurality of said first logic circuits divided for output over a plurality of times in a time-divisional manner.

Claim 15

The semiconductor device according to claim 7 , wherein the plurality of registers of each group are further divided into a plurality of sub-groups, further comprising a determination circuit determining whether the logic of the output signals of the plurality of registers of each group matches or not, and selecting an unmatching group, wherein said output circuit further provides an output signal of at least one register in each sub-group belonging to the group selected by said determination circuit in said test operation.

Claim 16

The semiconductor device according to claim 13 , wherein said test operation is divided into first and second tests, wherein said output circuit provides an output signal of at least one register of each group outside in said first test, and provides an output signal of at least one register out of each sub-group belonging to the group selected by said determination circuit outside in said second test.

Claim 17

The semiconductor device according to claim 13 , wherein said output circuit provides output signals of a plurality of registers of each sub-group belonging to the group selected by said determination circuit divided for output over a plurality of times in a time-divisional manner in said test operation.

Claim 18

The semiconductor device according to claim 13 , wherein any register in each sub-group is preselected, wherein said output circuit provides an output signal of the preselected register of each sub-group belonging to the group selected by said determination circuit outside in said test operation.

Claim 19

The semiconductor device according to claim 16 , wherein said output circuit provides output signals of the preselected plurality of registers from said plurality of sub-groups divided for output over a plurality of times in a time-divisional manner.

Claim 20

The semiconductor device according to claim 7 , wherein each of the plurality of registers of a first stage side out of the plurality of registers of said shift register holds said signal of the first logic, and each of the other registers holds said signal of the second logic.

Claim 21

The semiconductor device according to claim 7 , wherein any one of the plurality of registers of said shift register holds said signal of the first logic, and each of the other registers holds said signal of the second logic.

Claim 22

The semiconductor device according to claim 7 , wherein said internal circuit includes a memory circuit from which stored data is read out in synchronization with said internal clock signal, wherein said output circuit comprises a switch circuit receiving read out data of said memory circuit and an output signal of at least one register of each said group to pass read out data of said memory cell in said normal operation, and to pass the output signal of at least one register of said each group in said test operation, and a data output circuit providing read out data of said memory circuit and the output signal of at least one register of said each group passing said switch circuit outside.