US6157690A
Expired / Lapsed
US
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Digital PLL circuit
Assignee: Renesas Electronics Corp
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Filing: 1998-03-26
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Granted: 2000-12-05
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Expires: 2018-03-26
Abstract
Abstract A PLL circuit comprises a delay control signal generator for increment/decrement of a delay control signal based on a phase lead/lag of an internal clock signal with respect to a reference clock signal, a variable delay circuit for delaying the reference clock signal based on the delay control signal to generate the internal clock signal, and an enable signal generator for retarding the delay control signal generator to increment or decrement the delay control signal for a time length corresponding to the amount of the phase error.
Inventors
- 👤 Satoshi Yoneda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:31
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0802; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/085; H03L7/089; H04; H04L; H04L7/00; H04L7/0016; H04L7/0033; H04L7/0037
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
193 words
A digital phase locked loop (PLL) circuit comprising a phase comparator for comparing an internal clock signal against a reference clock signal to generate a phase lead/lag signal representing whether said internal clock signal leads or lags in phase with respect to said reference clock signal and a phase error signal representing a phase error between said internal clock signal and said reference clock signal, a delay controller for receiving said phase lead/lag signal to increment or decrement a delay control signal based on said phase lead/lag signal, a variable delay circuit for receiving said reference clock signal and said delay control signal to generate said internal clock signal having a phase delay based on said delay control signal with respect to said reference clock signal, and an enable signal generator for receiving said phase error signal to generate an enable signal for allowing or retarding said delay control signal based on said phase error to increment or decrement said delay control signal wherein said enable signal generator further receives said phase lead/lag signal, and said enable signal retards said delay control signal generator for a time length based on said phase error.
Claim 2
Dependent Claim
193 words
A digital phase locked loop (PLL) circuit comprising a phase comparator for comparing an internal clock signal against a reference clock signal to generate a phase lead/lag signal representing whether said internal clock signal leads or lags in phase with respect to said reference clock signal and a phase error signal representing a phase error between said internal clock signal and said reference clock signal, a delay controller for receiving said phase lead/lag signal to increment or decrement a delay control signal based on said phase lead/lag signal, a variable delay circuit for receiving said reference clock signal and said delay control signal to generate said internal clock signal having a phase delay based on said delay control signal with respect to said reference clock signal, and an enable signal generator for receiving said phase error signal to generate an enable signal for allowing or retarding said delay control signal based on said phase error to increment or decrement said delay control signal wherein said enable signal generator further receives said phase lead/lag signal, and said enable signal retards said delay control signal generator for a time length based on said phase error.
Claim 3
Dependent Claim
248 words
A digital phase locked loop (PLL) circuit comprising a phase comparator for comparing an internal clock signal against a reference clock signal to generate a phase lead/lag signal representing whether said internal clock signal leads or lags in phase with respect to said reference clock signal and a phase error signal representing a phase error between said internal clock signal and said reference clock signal, a delay controller for receiving said phase lead/lag signal to increment or decrement a delay control signal based on said phase lead/lag signal, a variable delay circuit for receiving said reference clock signal and said delay control signal to generate said internal clock signal having a phase delay based on said delay control signal with respect to said reference clock signal, and an enable signal generator for receiving said phase error signal to generate an enable signal for allowing or retarding said delay control signal based on said phase error to increment or decrement said delay control signal, wherein said enable signal generator further receives said phase lead/lag signal, and said enable signal retards said delay control signal generator for a time length based on said phase error and said phase error signal includes a first error signal representing a first phase error and a second error signal representing a second phase error, and said enable signal retards said delay control signal for a first time length or a second time length based on said first phase error or said second phase error.
Claim 4
Dependent Claim
248 words
A digital phase locked loop (PLL) circuit comprising a phase comparator for comparing an internal clock signal against a reference clock signal to generate a phase lead/lag signal representing whether said internal clock signal leads or lags in phase with respect to said reference clock signal and a phase error signal representing a phase error between said internal clock signal and said reference clock signal, a delay controller for receiving said phase lead/lag signal to increment or decrement a delay control signal based on said phase lead/lag signal, a variable delay circuit for receiving said reference clock signal and said delay control signal to generate said internal clock signal having a phase delay based on said delay control signal with respect to said reference clock signal, and an enable signal generator for receiving said phase error signal to generate an enable signal for allowing or retarding said delay control signal based on said phase error to increment or decrement said delay control signal, wherein said enable signal generator further receives said phase lead/lag signal, and said enable signal retards said delay control signal generator for a time length based on said phase error and said phase error signal includes a first error signal representing a first phase error and a second error signal representing a second phase error, and said enable signal retards said delay control signal for a first time length or a second time length based on said first phase error or said second phase error.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-05 | 2004-06-05 | 2004-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-05 | 2008-06-05 | 2008-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-05 | 2012-06-05 | 2012-12-05 | $7700.00 | Window Closed / Lapsed |