US5771264A
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US
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Digital delay lock loop for clock signal frequency multiplication
Assignee: Altera Corp
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Filing: 1997-01-07
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Granted: 1998-06-23
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Expires: 2017-01-07
Abstract
Abstract A digital delay lock loop for generating frequency multiples of an input clock signal includes a programmable digital oscillator, a phase comparator, a programmable counter and delay control logic. The programmable digital oscillator is a ring connected programmable delay line and inverter which together generate an output clock signal having a frequency which depends upon the time delay of the programmable delay line. The phase comparator compares the phase of the output clock signal to that of a reference clock signal and generates a phase error signal which represents the phase difference between such signals. The programmable counter, programmed and reprogrammed with the arrival of every reference clock signal pulse, counts the output clock signal pulses to generate a count signal. The delay control logic, in response to the phase error signal and count signal, programs the time delay of the programmable delay line, thereby causing the output clock signal frequency to be the desired multiple of the reference clock frequency.
Inventors
- 👤 Chris Lane
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:08
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0995; H03L7/16; H03L7/18; H03L7/181; H03L7/085; H03L7/089
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
271 words
An apparatus including a digital delay lock loop for generating frequency multiples of an input clock signal, comprising: a programmable digital delay oscillator circuit configured to receive at least one delay control signal and a reference clock signal and in accordance therewith provide an output clock signal, wherein said reference clock signal includes a reference clock signal frequency, said output clock signal includes an output clock signal frequency, said programmable digital delay oscillator circuit includes an internal signal delay which is controlled by said at least one delay control signal and said output clock signal frequency is controlled by said internal signal delay; a phase comparison circuit, coupled to said programmable digital delay oscillator circuit, configured to receive said reference clock signal and said output clock signal and in accordance therewith provide at least one phase comparison result signal, wherein said reference clock signal further includes a reference clock signal phase, said output clock signal further includes an output clock signal phase and said at least one phase comparison result signal represents a difference between said reference clock signal phase and said output clock signal phase; a digital counter, coupled to said programmable digital delay oscillator circuit, configured to receive said reference clock signal and said output clock signal and in accordance therewith provide at least one digital count signal; and a delay controller, coupled to said programmable digital delay oscillator circuit, said phase comparison circuit and said digital counter, configured to receive said at least one phase comparison result signal and said at least one digital count signal and in accordance therewith provide said at least one delay control signal.
Claim 2
Independent Claim
271 words
An apparatus including a digital delay lock loop for generating frequency multiples of an input clock signal, comprising: a programmable digital delay oscillator circuit configured to receive at least one delay control signal and a reference clock signal and in accordance therewith provide an output clock signal, wherein said reference clock signal includes a reference clock signal frequency, said output clock signal includes an output clock signal frequency, said programmable digital delay oscillator circuit includes an internal signal delay which is controlled by said at least one delay control signal and said output clock signal frequency is controlled by said internal signal delay; a phase comparison circuit, coupled to said programmable digital delay oscillator circuit, configured to receive said reference clock signal and said output clock signal and in accordance therewith provide at least one phase comparison result signal, wherein said reference clock signal further includes a reference clock signal phase, said output clock signal further includes an output clock signal phase and said at least one phase comparison result signal represents a difference between said reference clock signal phase and said output clock signal phase; a digital counter, coupled to said programmable digital delay oscillator circuit, configured to receive said reference clock signal and said output clock signal and in accordance therewith provide at least one digital count signal; and a delay controller, coupled to said programmable digital delay oscillator circuit, said phase comparison circuit and said digital counter, configured to receive said at least one phase comparison result signal and said at least one digital count signal and in accordance therewith provide said at least one delay control signal.
Claim 3
Dependent Claim
85 words
The apparatus of claim 1, wherein said programmable digital delay oscillator circuit comprises: a programmable digital delay line configured to be programmed in accordance with said at least one delay control signal and clocked in accordance with said reference clock signal and in accordance therewith receive and delay an inverted output clock signal to provide said output clock signal; and an inverter, coupled to said programmable digital delay line, configured to receive and invert said output clock signal to provide said inverted output clock signal.
Claim 4
Dependent Claim
68 words
The apparatus of claim 1, wherein said phase comparison circuit comprises: a feedback circuit configured to receive and process said output clock signal and in accordance therewith provide a feedback clock signal; and a phase comparator, coupled to said feedback circuit, configured to receive and compare said reference clock signal and said feedback clock signal and in accordance therewith provide said at least one phase comparison result signal.
Claim 5
Dependent Claim
30 words
The apparatus of claim 3, wherein said feedback circuit comprises a frequency divider circuit configured to receive and frequency divide said output clock signal to provide said feedback clock signal.
Claim 6
Dependent Claim
25 words
The apparatus of claim 1, wherein said at least one digital count signal represents a count value which is indexed by said output clock signal.
Claim 7
Dependent Claim
28 words
The apparatus of claim 5, wherein said at least one digital count signal has an initial count value which is established in accordance with said reference clock signal.
Claim 8
Dependent Claim
32 words
The apparatus of claim 6, wherein said digital counter comprises a programmable digital counter and is further configured to receive at least one counter programming signal which represents said initial count value.
Claim 9
Dependent Claim
56 words
The apparatus of claim 1, wherein said delay controller comprises a plurality of digital logic gates and said at least one digital count signal includes at least one digital count signal value which selectively takes precedence over said at least one phase comparison result signal in said providing of said at least one delay control signal.
Claim 10
Independent Claim
296 words
A method of providing an apparatus including a digital delay lock loop for generating frequency multiples of an input clock signal, said method comprising the steps of: providing a programmable digital delay oscillator circuit for performing the step of receiving at least one delay control signal and a reference clock signal and in accordance therewith generating an output clock signal, wherein said reference clock signal includes a reference clock signal frequency, said output clock signal includes an output clock signal frequency, said programmable digital delay oscillator circuit includes an internal signal delay which is controlled by said at least one delay control signal and said output clock signal frequency is controlled by said internal signal delay; providing a phase comparison circuit, coupled to said programmable digital delay oscillator circuit, for performing the step of receiving said reference clock signal and said output clock signal and in accordance therewith generating at least one phase comparison result signal, wherein said reference clock signal further includes a reference clock signal phase, said output clock signal further includes an output clock signal phase and said at least one phase comparison result signal represents a difference between said reference clock signal phase and said output clock signal phase; providing a digital counter, coupled to said programmable digital delay oscillator circuit, for performing the step of receiving said reference clock signal and said output clock signal and in accordance therewith generating at least one digital count signal; and providing a delay controller, coupled to said programmable digital delay oscillator circuit, said phase comparison circuit and said digital counter, for performing the step of receiving said at least one phase comparison result signal and said at least one digital count signal and in accordance therewith generating said at least one delay control signal.
Claim 11
Independent Claim
296 words
A method of providing an apparatus including a digital delay lock loop for generating frequency multiples of an input clock signal, said method comprising the steps of: providing a programmable digital delay oscillator circuit for performing the step of receiving at least one delay control signal and a reference clock signal and in accordance therewith generating an output clock signal, wherein said reference clock signal includes a reference clock signal frequency, said output clock signal includes an output clock signal frequency, said programmable digital delay oscillator circuit includes an internal signal delay which is controlled by said at least one delay control signal and said output clock signal frequency is controlled by said internal signal delay; providing a phase comparison circuit, coupled to said programmable digital delay oscillator circuit, for performing the step of receiving said reference clock signal and said output clock signal and in accordance therewith generating at least one phase comparison result signal, wherein said reference clock signal further includes a reference clock signal phase, said output clock signal further includes an output clock signal phase and said at least one phase comparison result signal represents a difference between said reference clock signal phase and said output clock signal phase; providing a digital counter, coupled to said programmable digital delay oscillator circuit, for performing the step of receiving said reference clock signal and said output clock signal and in accordance therewith generating at least one digital count signal; and providing a delay controller, coupled to said programmable digital delay oscillator circuit, said phase comparison circuit and said digital counter, for performing the step of receiving said at least one phase comparison result signal and said at least one digital count signal and in accordance therewith generating said at least one delay control signal.
Claim 12
Dependent Claim
109 words
The method of claim 9, wherein said step of providing a programmable digital delay oscillator circuit comprises the steps of: providing a programmable digital delay line for performing the step of programming said programmable digital delay line in accordance with said at least one delay control signal and clocking said programmable digital delay line in accordance with said reference clock signal and in accordance therewith receiving and delaying an inverted output clock signal to generate said output clock signal; and providing an inverter, coupled to said programmable digital delay line, for performing the step of receiving and inverting said output clock signal to generate said inverted output clock signal.
Claim 13
Dependent Claim
83 words
The method of claim 9, wherein said step of providing a phase comparison circuit comprises the steps of: providing a feedback circuit for performing the step of receiving and processing said output clock signal and in accordance therewith generating a feedback clock signal; and providing a phase comparator, coupled to said feedback circuit, for performing the step of receiving and comparing said reference clock signal and said feedback clock signal and in accordance therewith generating said at least one phase comparison result signal.
Claim 14
Dependent Claim
38 words
The method of claim 11, wherein said step of providing a feedback circuit comprises providing a frequency divider circuit for performing the step of receiving and frequency dividing said output clock signal to generate said feedback clock signal.
Claim 15
Dependent Claim
25 words
The method of claim 9, wherein said at least one digital count signal represents a count value which is indexed by said output clock signal.
Claim 16
Dependent Claim
28 words
The method of claim 13, wherein said at least one digital count signal has an initial count value which is established in accordance with said reference clock signal.
Claim 17
Dependent Claim
42 words
The method of claim 14, wherein said step of providing a digital counter comprises providing a programmable digital counter for performing the step of programming said programmable digital counter with at least one counter programming signal which represents said initial count value.
Claim 18
Dependent Claim
61 words
The method of claim 9, wherein said step of providing a delay controller comprises providing a plurality of digital logic gates and said at least one digital count signal includes at least one digital count signal value which selectively takes precedence over said at least one phase comparison result signal in said generating of said at least one delay control signal.
Claim 19
Independent Claim
211 words
A method of generating frequency multiples of an input clock signal with a digital delay lock loop, said method comprising the steps of: receiving at least one delay control signal and a reference clock signal and in accordance therewith generating an output clock signal, wherein said reference clock signal includes a reference clock signal frequency, said output clock signal includes an output clock signal frequency and said output clock signal frequency is controlled by a signal delay which is controlled by said at least one delay control signal; receiving said reference clock signal and said output clock signal and in accordance therewith generating at least one phase comparison result signal, wherein said reference clock signal further includes a reference clock signal phase, said output clock signal further includes an output clock signal phase and said at least one phase comparison result signal represents a difference between said reference clock signal phase and said output clock signal phase; receiving said reference clock signal and receiving and counting said output clock signal and in accordance therewith generating at least one digital count signal; and receiving said at least one phase comparison result signal and said at least one digital count signal and in accordance therewith generating said at least one delay control signal.
Claim 20
Independent Claim
211 words
A method of generating frequency multiples of an input clock signal with a digital delay lock loop, said method comprising the steps of: receiving at least one delay control signal and a reference clock signal and in accordance therewith generating an output clock signal, wherein said reference clock signal includes a reference clock signal frequency, said output clock signal includes an output clock signal frequency and said output clock signal frequency is controlled by a signal delay which is controlled by said at least one delay control signal; receiving said reference clock signal and said output clock signal and in accordance therewith generating at least one phase comparison result signal, wherein said reference clock signal further includes a reference clock signal phase, said output clock signal further includes an output clock signal phase and said at least one phase comparison result signal represents a difference between said reference clock signal phase and said output clock signal phase; receiving said reference clock signal and receiving and counting said output clock signal and in accordance therewith generating at least one digital count signal; and receiving said at least one phase comparison result signal and said at least one digital count signal and in accordance therewith generating said at least one delay control signal.
Claim 21
Dependent Claim
97 words
The apparatus of claim 17, wherein said step of receiving at least one delay control signal and a reference clock signal and in accordance therewith generating an output clock signal comprises the steps of: programming a programmable digital delay line in accordance with said at least one delay control signal and clocking said programmable digital delay line in accordance with said reference clock signal and in accordance therewith receiving and delaying an inverted output clock signal to generate said output clock signal; and receiving and inverting said output clock signal to generate said inverted output clock signal.
Claim 22
Dependent Claim
77 words
The apparatus of claim 17, wherein said step of receiving said reference clock signal and said output clock signal and in accordance therewith generating at least one phase comparison result signal comprises the steps of: receiving and processing said output clock signal and in accordance therewith generating a feedback clock signal; and receiving and comparing said reference clock signal and said feedback clock signal and in accordance therewith generating said at least one phase comparison result signal.
Claim 23
Dependent Claim
40 words
The apparatus of claim 19, wherein said step of receiving and processing said output clock signal and in accordance therewith generating a feedback clock signal comprises receiving and frequency dividing said output clock signal to generate said feedback clock signal.
Claim 24
Dependent Claim
25 words
The apparatus of claim 17, wherein said at least one digital count signal represents a count value which is indexed by said output clock signal.
Claim 25
Dependent Claim
28 words
The apparatus of claim 21, wherein said at least one digital count signal has an initial count value which is established in accordance with said reference clock signal.
Claim 26
Dependent Claim
64 words
The apparatus of claim 22, wherein said step of receiving said reference clock signal and receiving and counting said output clock signal and in accordance therewith generating at least one digital count signal comprises receiving at least one programming signal which represents said initial count value and in accordance therewith counting said output clock signal to generate said at least one digital count signal.
Claim 27
Dependent Claim
45 words
The apparatus of claim 17, wherein said at least one digital count signal includes at least one digital count signal value which selectively takes precedence over said at least one phase comparison result signal in said generating of said at least one delay control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-22 | 2001-12-22 | 2002-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-22 | 2005-12-22 | 2006-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-22 | 2009-12-22 | 2010-06-23 | $7700.00 | Window Closed / Lapsed |