US6292016B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable logic with on-chip DLL or PLL to distribute clock
Assignee: Altera Corp
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Filing: 2000-06-05
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Granted: 2001-09-18
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Expires: 2020-06-05
Abstract
Abstract A programmable logic device or field programmable gate array includes an on-chip clock synchronization circuit to synchronize a reference or system clock signal. The clock synchronization circuit is a delay-locked loop (DLL) circuit in one implementation and a phase locked loop (PLL) circuit in another implementation. The DLL or PLL circuits may be analog or digital. The clock synchronization circuit generates a synchronized clock signal that is distributed throughout the programmable integrated circuit. The synchronized clock signal is programmably connected to the programmable logic elements or logic array blocks (LABs) of the integrated circuit. The clock synchronization circuit reduces or minimizes clock skew when distributing a clock signal within the integrated circuit. The clock synchronization circuit improves the overall performance of the programmable logic integrated circuit.
Inventors
- 👤 David E. Jefferson
- 👤 L. Todd Cope
- 👤 Srinivas Reddy
- 👤 Richard G. Cliff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:04
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/1774; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H03K19/17724; H03K19/17732; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/085; H03L7/087; H03L7/0818
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
133 words
A programmable logic integrated circuit comprising: a delay locked loop circuit coupled to an external clock input to receive an external clock of the programmable logic integrated circuit, wherein the delay locked loop circuit generates a synchronized clock; a first plurality of logic array blocks configurable to implement logic functions in a first location of the integrated circuit; a second plurality of logic array blocks configurable to implement logic functions in a second location of the integrated circuit; a first multiplexer to selectably couple the external clock or the synchronized clock to a first clock input line of the first plurality of logic array blocks; and a second multiplexer to selectably couple the external clock or the synchronized clock to a second clock input line of the second plurality of logic array blocks.
Claim 2
Dependent Claim
133 words
A programmable logic integrated circuit comprising: a delay locked loop circuit coupled to an external clock input to receive an external clock of the programmable logic integrated circuit, wherein the delay locked loop circuit generates a synchronized clock; a first plurality of logic array blocks configurable to implement logic functions in a first location of the integrated circuit; a second plurality of logic array blocks configurable to implement logic functions in a second location of the integrated circuit; a first multiplexer to selectably couple the external clock or the synchronized clock to a first clock input line of the first plurality of logic array blocks; and a second multiplexer to selectably couple the external clock or the synchronized clock to a second clock input line of the second plurality of logic array blocks.
Claim 3
Dependent Claim
133 words
A programmable logic integrated circuit comprising: a phase locked loop circuit coupled to an external clock input to receive an external clock of the programmable logic integrated circuit, wherein the phase locked loop circuit generates a synchronized clock; a first plurality of logic array blocks configurable to implement logic functions in a first location of the integrated circuit; a second plurality of logic array blocks configurable to implement logic functions in a second location of the integrated circuit; a first multiplexer to selectably couple the external clock or the synchronized clock to a first clock input line of the first plurality of logic array blocks; and a second multiplexer to selectably couple the external clock or the synchronized clock to a second clock input line of the second plurality of logic array blocks.
Claim 4
Dependent Claim
133 words
A programmable logic integrated circuit comprising: a phase locked loop circuit coupled to an external clock input to receive an external clock of the programmable logic integrated circuit, wherein the phase locked loop circuit generates a synchronized clock; a first plurality of logic array blocks configurable to implement logic functions in a first location of the integrated circuit; a second plurality of logic array blocks configurable to implement logic functions in a second location of the integrated circuit; a first multiplexer to selectably couple the external clock or the synchronized clock to a first clock input line of the first plurality of logic array blocks; and a second multiplexer to selectably couple the external clock or the synchronized clock to a second clock input line of the second plurality of logic array blocks.
Claim 5
Dependent Claim
165 words
A programmable logic integrated circuit comprising: a delay locked loop circuit coupled to an external clock input to receive an external clock of the programmable logic integrated circuit, wherein the delay locked loop circuit generates a synchronized clock; a first plurality of logic array blocks configurable to implement logic functions in a first location of the integrated circuit; a second plurality of logic array blocks configurable to implement logic functions in a second location of the integrated circuit; a first multiplexer to selectably couple the external clock or the synchronized clock to a first clock input line of the first plurality of logic array blocks; a second multiplexer to selectably couple the external clock or the synchronized clock to a second clock input line of the second plurality of logic array blocks; a first delay element, coupled between the synchronized clock and an input to the first multiplexer; and a second delay element, coupled between the synchronized clock and an input to the second multiplexer.
Claim 6
Dependent Claim
165 words
A programmable logic integrated circuit comprising: a delay locked loop circuit coupled to an external clock input to receive an external clock of the programmable logic integrated circuit, wherein the delay locked loop circuit generates a synchronized clock; a first plurality of logic array blocks configurable to implement logic functions in a first location of the integrated circuit; a second plurality of logic array blocks configurable to implement logic functions in a second location of the integrated circuit; a first multiplexer to selectably couple the external clock or the synchronized clock to a first clock input line of the first plurality of logic array blocks; a second multiplexer to selectably couple the external clock or the synchronized clock to a second clock input line of the second plurality of logic array blocks; a first delay element, coupled between the synchronized clock and an input to the first multiplexer; and a second delay element, coupled between the synchronized clock and an input to the second multiplexer.
Claim 7
Dependent Claim
165 words
A programmable logic integrated circuit comprising: a phase locked loop circuit coupled to an external clock input to receive an external clock of the programmable logic integrated circuit, wherein the phase locked loop circuit generates a synchronized clock; a first plurality of logic array blocks configurable to implement logic functions in a first location of the integrated circuit; a second plurality of logic array blocks configurable to implement logic functions in a second location of the integrated circuit; a first multiplexer to selectably couple the external clock or the synchronized clock to a first clock input line of the first plurality of logic array blocks; a second multiplexer to selectably couple the external clock or the synchronized clock to a second clock input line of the second plurality of logic array blocks; a first delay element, coupled between the synchronized clock and an input to the first multiplexer; and a second delay element, coupled between the synchronized clock and an input to the second multiplexer.
Claim 8
Dependent Claim
165 words
A programmable logic integrated circuit comprising: a phase locked loop circuit coupled to an external clock input to receive an external clock of the programmable logic integrated circuit, wherein the phase locked loop circuit generates a synchronized clock; a first plurality of logic array blocks configurable to implement logic functions in a first location of the integrated circuit; a second plurality of logic array blocks configurable to implement logic functions in a second location of the integrated circuit; a first multiplexer to selectably couple the external clock or the synchronized clock to a first clock input line of the first plurality of logic array blocks; a second multiplexer to selectably couple the external clock or the synchronized clock to a second clock input line of the second plurality of logic array blocks; a first delay element, coupled between the synchronized clock and an input to the first multiplexer; and a second delay element, coupled between the synchronized clock and an input to the second multiplexer.
Claim 9
Dependent Claim
179 words
A programmable logic integrated circuit comprising: a delay locked loop circuit coupled to an external clock input to receive an external clock of the programmable logic integrated circuit, wherein the delay locked loop circuit generates a synchronized clock; a first plurality of logic array blocks configurable to implement logic functions in a first location of the integrated circuit; a second plurality of logic array blocks configurable to implement logic functions in a second location of the integrated circuit; a first multiplexer to selectably couple the external clock or the synchronized clock to a first clock input line of the first plurality of logic array blocks; a second multiplexer to selectably couple the external clock or the synchronized clock to a second clock input line of the second plurality of logic array blocks; a third plurality of logic array blocks configurable to implement logic functions in a third location of the integrated circuit; and a third multiplexer to selectively couple the external clock or the synchronized clock to a third clock line of the third plurality of logic array blocks.
Claim 10
Dependent Claim
179 words
A programmable logic integrated circuit comprising: a delay locked loop circuit coupled to an external clock input to receive an external clock of the programmable logic integrated circuit, wherein the delay locked loop circuit generates a synchronized clock; a first plurality of logic array blocks configurable to implement logic functions in a first location of the integrated circuit; a second plurality of logic array blocks configurable to implement logic functions in a second location of the integrated circuit; a first multiplexer to selectably couple the external clock or the synchronized clock to a first clock input line of the first plurality of logic array blocks; a second multiplexer to selectably couple the external clock or the synchronized clock to a second clock input line of the second plurality of logic array blocks; a third plurality of logic array blocks configurable to implement logic functions in a third location of the integrated circuit; and a third multiplexer to selectively couple the external clock or the synchronized clock to a third clock line of the third plurality of logic array blocks.
Claim 11
Dependent Claim
179 words
A programmable logic integrated circuit comprising: a phase locked loop circuit coupled to an external clock input to receive an external clock of the programmable logic integrated circuit, wherein the phase locked loop circuit generates a synchronized clock; a first plurality of logic array blocks configurable to implement logic functions in a first location of the integrated circuit; a second plurality of logic array blocks configurable to implement logic functions in a second location of the integrated circuit; a first multiplexer to selectably couple the external clock or the synchronized clock to a first clock input line of the first plurality of logic array blocks; a second multiplexer to selectably couple the external clock or the synchronized clock to a second clock input line of the second plurality of logic array blocks; a third plurality of logic array blocks configurable to implement logic functions in a third location of the integrated circuit; and a third multiplexer to selectively couple the external clock or the synchronized clock to a third clock line of the third plurality of logic array blocks.
Claim 12
Dependent Claim
179 words
A programmable logic integrated circuit comprising: a phase locked loop circuit coupled to an external clock input to receive an external clock of the programmable logic integrated circuit, wherein the phase locked loop circuit generates a synchronized clock; a first plurality of logic array blocks configurable to implement logic functions in a first location of the integrated circuit; a second plurality of logic array blocks configurable to implement logic functions in a second location of the integrated circuit; a first multiplexer to selectably couple the external clock or the synchronized clock to a first clock input line of the first plurality of logic array blocks; a second multiplexer to selectably couple the external clock or the synchronized clock to a second clock input line of the second plurality of logic array blocks; a third plurality of logic array blocks configurable to implement logic functions in a third location of the integrated circuit; and a third multiplexer to selectively couple the external clock or the synchronized clock to a third clock line of the third plurality of logic array blocks.
Claim 13
Dependent Claim
57 words
The programmable logic integrated circuit of claim 5 further comprising: a fourth plurality of logic array blocks configurable to implement logic functions in a fourth location of the integrated circuit; and a fourth multiplexer to selectively couple the external clock or the synchronized clock to a fourth clock line of the fourth plurality of logic array blocks.
Claim 14
Dependent Claim
57 words
The programmable logic integrated circuit of claim 6 further comprising: a fourth plurality of logic array blocks configurable to implement logic functions in a fourth location of the integrated circuit; and a fourth multiplexer to selectively couple the external clock or the synchronized clock to a fourth clock line of the fourth plurality of logic array blocks.
Claim 15
Dependent Claim
57 words
The programmable logic integrated circuit of claim 7 further comprising: a fifth plurality of logic array blocks configurable to implement logic functions in a fifth location of the integrated circuit; and a fifth multiplexer to selectively couple the external clock or the synchronized clock to a fifth clock line of the fifth plurality of logic array blocks.
Claim 16
Dependent Claim
57 words
The programmable logic integrated circuit of claim 8 further comprising: a fifth plurality of logic array blocks configurable to implement logic functions in a fifth location of the integrated circuit; and a fifth multiplexer to selectively couple the external clock or the synchronized clock to a fifth clock line of the fifth plurality of logic array blocks.
Claim 17
Dependent Claim
26 words
The programmable logic integrated circuit of claim 5 further comprising: a third delay element, coupled between the synchronized clock and an input to the third multiplexer.
Claim 18
Dependent Claim
26 words
The programmable logic integrated circuit of claim 6 further comprising: a third delay element, coupled between the synchronized clock and an input to the third multiplexer.
Claim 19
Dependent Claim
57 words
The programmable logic integrated circuit of claim 11 further comprising: a fourth plurality of logic array blocks configurable to implement logic functions in a fourth location of the integrated circuit; and a fourth multiplexer to selectively couple the external clock or the synchronized clock to a fourth clock line of the fourth plurality of logic array blocks.
Claim 20
Dependent Claim
57 words
The programmable logic integrated circuit of claim 12 further comprising: a fourth plurality of logic array blocks configurable to implement logic functions in a fourth location of the integrated circuit; and a fourth multiplexer to selectively couple the external clock or the synchronized clock to a fourth clock line of the fourth plurality of logic array blocks.
Claim 21
Dependent Claim
57 words
The programmable logic integrated circuit of claim 13 further comprising: a fifth plurality of logic array blocks configurable to implement logic functions in a fifth location of the integrated circuit; and a fifth multiplexer to selectively couple the external clock or the synchronized clock to a fifth clock line of the fifth plurality of logic array blocks.
Claim 22
Dependent Claim
57 words
The programmable logic integrated circuit of claim 14 further comprising: a fifth plurality of logic array blocks configurable to implement logic functions in a fifth location of the integrated circuit; and a fifth multiplexer to selectively couple the external clock or the synchronized clock to a fifth clock line of the fifth plurality of logic array blocks.
Claim 23
Dependent Claim
45 words
The programmable logic integrated circuit of claim 1 further comprising: a first input buffer, coupled between the external clock input and an input to the first multiplexer; and a second input buffer, coupled between the external clock input and an input to the second multiplexer.
Claim 24
Dependent Claim
45 words
The programmable logic integrated circuit of claim 2 further comprising: a first input buffer, coupled between the external clock input and an input to the first multiplexer; and a second input buffer, coupled between the external clock input and an input to the second multiplexer.
Claim 25
Dependent Claim
26 words
The programmable logic integrated circuit of claim 17 wherein the first input buffer is further coupled between the external clock input and the delay locked loop.
Claim 26
Dependent Claim
26 words
The programmable logic integrated circuit of claim 18 wherein the first input buffer is further coupled between the external clock input and the phase locked loop.
Claim 27
Dependent Claim
78 words
A programmable logic integrated circuit comprising: a delay locked loop circuit coupled to an external clock input and generating a synchronized clock; a plurality of logic array blocks in n sections of the integrated circuit, wherein n is an integer; and n multiplexers, each coupled to the external clock and the synchronized clock, each selectively coupling the external clock or synchronized clock to logic array blocks in a respective one of the n sections of the integrated circuit.
Claim 28
Dependent Claim
78 words
A programmable logic integrated circuit comprising: a delay locked loop circuit coupled to an external clock input and generating a synchronized clock; a plurality of logic array blocks in n sections of the integrated circuit, wherein n is an integer; and n multiplexers, each coupled to the external clock and the synchronized clock, each selectively coupling the external clock or synchronized clock to logic array blocks in a respective one of the n sections of the integrated circuit.
Claim 29
Dependent Claim
34 words
The programmable logic integrated circuit of claim 21 further comprising: n delay elements, a respective one of n delay elements is coupled between the synchronized clock and a respective one of the n multiplexers.
Claim 30
Dependent Claim
35 words
The programmable logic integrated circuit of claim 21 further comprising: n input buffers, a respective one of n input buffers is coupled between the external clock input and a respective one of the n multiplexers.
Claim 31
Dependent Claim
35 words
The programmable logic integrated circuit of claim 22 further comprising: n input buffers, a respective one of n input buffers is coupled between the external clock input and a respective one of the n multiplexers.
Claim 32
Dependent Claim
24 words
The programmable logic integrated circuit of claim 21 wherein one of the n input buffers is further coupled to the delay locked loop circuit.
Claim 33
Dependent Claim
24 words
The programmable logic integrated circuit of claim 24 wherein one of the n input buffers is further coupled to the delay locked loop circuit.
Claim 34
Dependent Claim
78 words
A programmable logic integrated circuit comprising: a phase locked loop circuit coupled to an external clock input and generating a synchronized clock; a plurality of logic array blocks in n sections of the integrated circuit, wherein n is an integer; and n multiplexers, each coupled to the external clock and the synchronized clock, each selectively coupling the external clock or synchronized clock to logic array blocks in a respective one of the n sections of the integrated circuit.
Claim 35
Dependent Claim
78 words
A programmable logic integrated circuit comprising: a phase locked loop circuit coupled to an external clock input and generating a synchronized clock; a plurality of logic array blocks in n sections of the integrated circuit, wherein n is an integer; and n multiplexers, each coupled to the external clock and the synchronized clock, each selectively coupling the external clock or synchronized clock to logic array blocks in a respective one of the n sections of the integrated circuit.
Claim 36
Dependent Claim
34 words
The programmable logic integrated circuit of claim 27 further comprising: n delay elements, a respective one of n delay elements is coupled between the synchronized clock and a respective one of the n multiplexers.
Claim 37
Dependent Claim
35 words
The programmable logic integrated circuit of claim 27 further comprising: n input buffers, a respective one of n input buffers is coupled between the external clock input and a respective one of the n multiplexers.
Claim 38
Dependent Claim
35 words
The programmable logic integrated circuit of claim 28 further comprising: n input buffers, a respective one of n input buffers is coupled between the external clock input and a respective one of the n multiplexers.
Claim 39
Dependent Claim
24 words
The programmable logic integrated circuit of claim 27 wherein one of the n input buffers is further coupled to the phase locked loop circuit.
Claim 40
Dependent Claim
24 words
The programmable logic integrated circuit of claim 30 wherein one of the n input buffers is further coupled to the phase locked loop circuit.
Claim 41
Dependent Claim
17 words
The programmable logic integrated circuit of claim 21 wherein n is 1, 2, 3, 4, or 5.
Claim 42
Dependent Claim
17 words
The programmable logic integrated circuit of claim 27 wherein n is 1, 2, 3, 4, or 5.
Claim 43
Dependent Claim
12 words
The programmable logic integrated circuit of claim 21 wherein n is 2.
Claim 44
Dependent Claim
14 words
The programmable logic integrated circuit of claim 21 wherein n is 4 or greater.
Claim 45
Dependent Claim
12 words
The programmable logic integrated circuit of claim 27 wherein n is 2.
Claim 46
Dependent Claim
14 words
The programmable logic integrated circuit of claim 27 wherein n is 4 or greater.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-09-17 | 2005-03-19 | 2005-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-09-17 | 2009-03-19 | 2009-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-09-17 | 2013-03-19 | 2013-09-18 | $7700.00 | Window Closed / Lapsed |