US5644251A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits
Assignee: LSI Corp
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Filing: 1995-09-26
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Granted: 1997-07-01
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Expires: 2015-09-26
Abstract
Abstract An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.
Inventors
- 👤 Michael Colwell
- 👤 Rochit Rajsuman
- 👤 Ray Abrishami
- 👤 Zarir B. Sarkari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:57
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/3004; G01R31/3008
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
89 words
A switchable pull-up circuit for a signal line of an integrated circuit, comprising: switching means connected between said signal line and a source of potential of said integrated circuit; and IDDQ testing means for applying a control signal to said switching means having a first selectable value that enables said switching means to pull said signal line to said source of potential, and a second selectable value that causes said switching means to disconnect said signal line from said source of potential for IDDQ testing of said integrated circuit.
Claim 2
Dependent Claim
89 words
A switchable pull-up circuit for a signal line of an integrated circuit, comprising: switching means connected between said signal line and a source of potential of said integrated circuit; and IDDQ testing means for applying a control signal to said switching means having a first selectable value that enables said switching means to pull said signal line to said source of potential, and a second selectable value that causes said switching means to disconnect said signal line from said source of potential for IDDQ testing of said integrated circuit.
Claim 3
Dependent Claim
22 words
The switchable pull-up circuit of claim 1 wherein said source of potential comprises a Vdd voltage circuit source of said integrated circuit.
Claim 4
Dependent Claim
14 words
The switchable pull-up circuit of claim 1 wherein said switching means is a FET.
Claim 5
Dependent Claim
14 words
The switchable pull-up circuit of claim 3 wherein said FET is a p-channel FET.
Claim 6
Dependent Claim
20 words
The switchable pull-up circuit of claim 3 wherein said control signal is connected to an input gate of said FET.
Claim 7
Independent Claim
88 words
A method of controlling switching means connected between a signal line and a source of potential of an integrated circuit, comprising the steps of: applying a control signal to said switching means having a first selectable value that enable said switching means to pull said signal line to said source of potential; and applying said control signal to said switching means having a second selectable value that causes said switching means to disconnect said signal line from said source of potential for IDDQ testing of said integrated circuit.
Claim 8
Independent Claim
88 words
A method of controlling switching means connected between a signal line and a source of potential of an integrated circuit, comprising the steps of: applying a control signal to said switching means having a first selectable value that enable said switching means to pull said signal line to said source of potential; and applying said control signal to said switching means having a second selectable value that causes said switching means to disconnect said signal line from said source of potential for IDDQ testing of said integrated circuit.
Claim 9
Dependent Claim
38 words
The method of claim 6 wherein the second method step of applying said control signal includes: providing a boundary scan test system; and causing said boundary scan test system to apply said control signal to said switching means.
Claim 10
Dependent Claim
44 words
The method of claim 6 further including the step of applying another control signal to said switching means to effectively connect said signal line to said source of potential of said integrated circuit through said switching means during normal operation of said integrated circuit.
Claim 11
Dependent Claim
19 words
The method of claim 6 wherein said source of potential comprises a Vdd voltage source of said integrated circuit.
Claim 12
Dependent Claim
12 words
The method of claim 6 wherein said switching means is a FET.
Claim 13
Dependent Claim
12 words
The method of claim 10 wherein said FET is a p-channel FET.
Claim 14
Dependent Claim
18 words
The method of claim 10 wherein said control signal input is connected to a gate of said FET.
Claim 15
Dependent Claim
97 words
An integrated circuit comprising: a source of potential; a plurality of signal lines; a plurality of switching means connected between said source of potential and said signal lines respectively; and IDDQ testing means for applying a control signal to said plurality of switching means having a first selectable value that enables said plurality of switching means to pull said signal lines to said source of potential respectively, and a second selectable value that causes said plurality of switching means to disconnect said signal lines from said source of potential respectively for IDDQ testing of said integrated circuit.
Claim 16
Dependent Claim
97 words
An integrated circuit comprising: a source of potential; a plurality of signal lines; a plurality of switching means connected between said source of potential and said signal lines respectively; and IDDQ testing means for applying a control signal to said plurality of switching means having a first selectable value that enables said plurality of switching means to pull said signal lines to said source of potential respectively, and a second selectable value that causes said plurality of switching means to disconnect said signal lines from said source of potential respectively for IDDQ testing of said integrated circuit.
Claim 17
Dependent Claim
37 words
The integrated circuit of claim 13 wherein said IDDQ testing means comprises: a boundary scan test system; and means for causing said boundary scan test system to apply said control signal to said plurality of switching means.
Claim 18
Dependent Claim
51 words
The integrated circuit of claim 13 wherein said control signal is operative to configure each of said plurality of switching means to effectively connect each of said signal lines to said source of potential of said integrated circuit through said plurality of switching means during normal operation of said integrated circuit.
Claim 19
Dependent Claim
20 words
The integrated circuit of claim 13 wherein said source of potential is a Vdd voltage source of said integrated circuit.
Claim 20
Dependent Claim
17 words
The integrated circuit of claim 13 wherein each of said plurality of switching means is a FET.
Claim 21
Dependent Claim
21 words
The integrated circuit of claim 17 wherein said control signal is connected to a gate of each one of said FET.
Claim 22
Independent Claim
80 words
A method of testing an integrated circuit, said method comprising the steps of: providing a switchable pull-up circuit including switching means connected between a signal line and a source of potential of said integrated circuit and responsive to a control signal; transmitting said control signal to said switching means so as to effectively disconnect said signal line from said source of potential; and testing said integrated circuit; wherein faults masked by said pull-up circuit can be detected during said testing.
Claim 23
Independent Claim
80 words
A method of testing an integrated circuit, said method comprising the steps of: providing a switchable pull-up circuit including switching means connected between a signal line and a source of potential of said integrated circuit and responsive to a control signal; transmitting said control signal to said switching means so as to effectively disconnect said signal line from said source of potential; and testing said integrated circuit; wherein faults masked by said pull-up circuit can be detected during said testing.
Claim 24
Dependent Claim
23 words
The method of claim 19 wherein said testing of said integrated circuit includes providing test signals on signal lines of said integrated circuit.
Claim 25
Dependent Claim
24 words
The method of claim 19 wherein said testing of said integrated circuit includes a measurement of a quiescent supply current of said integrated circuit.
Claim 26
Dependent Claim
153 words
A switchable pull-up/pull-down circuit for a signal line of an integrated circuit, comprising: a pull-up transistor for connecting the signal line to a first electrical source of potential; a pull-down transistor for connecting the signal line to a second electrical source of potential which is lower than the first electrical source of potential; and IDDQ testing means for applying an IDDQ testing control signal to the pull-up transistor and to the pull-down transistor having a first selectable value that enable the pull-up transistor to pull the signal line to the first electrical source of potential and enables the pull-down transistor to pull the signal line to the second electrical source of potential, and a second selectable value that causes the pull-up transistor and the pull-down transistor to disconnect the signal line from the first electrical source of potential and from the second electrical source of potential for IDDQ testing of the integrated circuit.
Claim 27
Dependent Claim
153 words
A switchable pull-up/pull-down circuit for a signal line of an integrated circuit, comprising: a pull-up transistor for connecting the signal line to a first electrical source of potential; a pull-down transistor for connecting the signal line to a second electrical source of potential which is lower than the first electrical source of potential; and IDDQ testing means for applying an IDDQ testing control signal to the pull-up transistor and to the pull-down transistor having a first selectable value that enable the pull-up transistor to pull the signal line to the first electrical source of potential and enables the pull-down transistor to pull the signal line to the second electrical source of potential, and a second selectable value that causes the pull-up transistor and the pull-down transistor to disconnect the signal line from the first electrical source of potential and from the second electrical source of potential for IDDQ testing of the integrated circuit.
Claim 28
Dependent Claim
24 words
The switchable pull-up/pull-down circuit of claim 22 wherein the first electrical source of potential comprises a Vdd voltage circuit source of the integrated circuit.
Claim 29
Dependent Claim
23 words
The switchable pull-up/pull-down circuit of claim 22 wherein the pull-up transistor comprises a first FET, and the pull-down transistor comprises a second FET.
Claim 30
Dependent Claim
31 words
The switchable pull-up/pull-down circuit of claim 24, in which the IDDQ testing means is connected to apply the testing control signal to gates of the first FET and the second FET.
Claim 31
Dependent Claim
31 words
The switchable pull-up/pull-down circuit of claim 24 wherein the IDDQ testing means comprises an invertor connected between the IDDQ testing means and one of the first FET and the second FET.
Claim 32
Dependent Claim
23 words
The switchable pull-up/pull-down circuit of claim 24 wherein the first FET is a p-channel FET and the second FET is an n-channel FET.
Claim 33
Dependent Claim
31 words
The switchable pull-up/pull-down circuit of claim 27 wherein the IDDQ testing means comprises an invertor connected between the IDDQ testing means and one of the first FET and the second FET.
Claim 34
Dependent Claim
36 words
The switchable pull-up/pull-down circuit of claim 28 wherein the invertor is connected between the IDDQ testing means and the second FET, the first selectable value is logic low, and the second selectable value is logic high.
Claim 35
Dependent Claim
36 words
The switchable pull-up/pull-down circuit of claim 28 wherein the invertor is connected between the IDDQ testing means and the first FET, the first selectable value is logic high, and the second selectable value is logic low.
Claim 36
Independent Claim
170 words
The method of performing IDDQ testing of an integrated circuit having a signal line, a pull-up transistor for connected the signal line to a first electrical source of potential, and a pull-down transistor for connecting the signal line to a second electrical source of potential which is lower than the first electrical source of potential, comprising the steps of: applying an IDDQ testing control signal to the pull-up transistor and to the pull-down transistor having a first selectable value that enables the pull-up transistor to pull the signal line to the first electrical source of potential and enables the pull-down transistor to pull the signal line to the second electrical source of potential; and applying the IDDQ testing control signal to the pull-up transistor and to the pull-down transistor having a second selectable value that causes the pull-up transistor and the pull-down transistor to disconnect the signal line from the firs electrical source of potential and from the second source of electrical potential for IDDQ testing of the integrated circuit.
Claim 37
Independent Claim
170 words
The method of performing IDDQ testing of an integrated circuit having a signal line, a pull-up transistor for connected the signal line to a first electrical source of potential, and a pull-down transistor for connecting the signal line to a second electrical source of potential which is lower than the first electrical source of potential, comprising the steps of: applying an IDDQ testing control signal to the pull-up transistor and to the pull-down transistor having a first selectable value that enables the pull-up transistor to pull the signal line to the first electrical source of potential and enables the pull-down transistor to pull the signal line to the second electrical source of potential; and applying the IDDQ testing control signal to the pull-up transistor and to the pull-down transistor having a second selectable value that causes the pull-up transistor and the pull-down transistor to disconnect the signal line from the firs electrical source of potential and from the second source of electrical potential for IDDQ testing of the integrated circuit.
Claim 38
Dependent Claim
92 words
A switchable pull circuit for a signal line of an integrated circuit, comprising: a pull transistor connected between the signal line and a source of potential of the integrated circuit; and IDDQ testing means for applying an IDDQ testing control signal to said pull transistor having a first selectable value that enables said pull transistor to pull said signal line to said source of potential, and a second selectable value that causes said pull transistor to disconnect said signal line from said source of potential for IDDQ testing of said integrated circuit.
Claim 39
Dependent Claim
92 words
A switchable pull circuit for a signal line of an integrated circuit, comprising: a pull transistor connected between the signal line and a source of potential of the integrated circuit; and IDDQ testing means for applying an IDDQ testing control signal to said pull transistor having a first selectable value that enables said pull transistor to pull said signal line to said source of potential, and a second selectable value that causes said pull transistor to disconnect said signal line from said source of potential for IDDQ testing of said integrated circuit.
Claim 40
Dependent Claim
16 words
The switchable pull circuit of claim 32, in which the pull transistor is a pull-down transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-30 | 2000-12-30 | 2001-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-30 | 2004-12-30 | 2005-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-30 | 2008-12-30 | 2009-07-01 | $7700.00 | Window Closed / Lapsed |