US6066969A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with DLL circuit avoiding excessive power consumption
Assignee: Socionext Inc
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Filing: 1998-08-06
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Granted: 2000-05-23
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Expires: 2018-08-06
Abstract
Abstract A semiconductor device includes a variable-delay circuit which delays an input-clock signal to generate a delay clock signal, a clock-control circuit which selects one of the input-clock signal and the delayed clock signal, an output circuit which outputs data in synchronism with a clock signal selected by the clock-control circuit, and a DLL circuit which adjusts a delay of the variable-delay circuit. The DLL circuit includes a delay-control circuit which adjusts the delay of the variable-delay circuit, and a clock-selection circuit which controls the clock-control circuit to select one of the input-clock signal and the delayed clock signal. The variable-delay circuit is controlled such that the delay is not increased when the input-clock signal is selected by the clock-selection circuit.
Inventors
- 👤 Kenichi Kawasaki
- 👤 Yasuharu Sato
- 👤 Hiroyoshi Tomita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:41
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03L7/081; H03L7/0802; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/16; H03L7/18; H03L7/197; H03L7/1972; H10; H10D; H10D84/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
122 words
A semiconductor device comprising: a variable-delay circuit which delays an input-clock signal to generate a delay clock signal; a clock-control circuit which selects one of the input-clock signal and the delayed clock signal; an output circuit which outputs data in synchronism with a clock signal selected by said clock-control circuit; and a DLL circuit which adjusts a delay of said variable-delay circuit, wherein said DLL circuit includes: a delay-control circuit which adjusts said delay of said variable-delay circuit; and a clock-selection circuit which controls said clock-control circuit to select one of the input-clock signal and the delayed clock signal, wherein said variable-delay circuit is controlled such that said delay is not increased when the input-clock signal is selected by said clock-selection circuit.
Claim 2
Dependent Claim
122 words
A semiconductor device comprising: a variable-delay circuit which delays an input-clock signal to generate a delay clock signal; a clock-control circuit which selects one of the input-clock signal and the delayed clock signal; an output circuit which outputs data in synchronism with a clock signal selected by said clock-control circuit; and a DLL circuit which adjusts a delay of said variable-delay circuit, wherein said DLL circuit includes: a delay-control circuit which adjusts said delay of said variable-delay circuit; and a clock-selection circuit which controls said clock-control circuit to select one of the input-clock signal and the delayed clock signal, wherein said variable-delay circuit is controlled such that said delay is not increased when the input-clock signal is selected by said clock-selection circuit.
Claim 3
Dependent Claim
30 words
The semiconductor device as claimed in claim 1, wherein said clock-selection circuit compares phases between said input-clock signal and said delayed-clock signal, and selects one which has an earlier phase.
Claim 4
Dependent Claim
65 words
The semiconductor device as claimed in claim 1, wherein said DLL circuit further includes: a frequency divider which applies a frequency division to said input-clock signal; and a loop-control unit which controls said delay-control circuit through a feedback loop based on a signal obtained by said frequency division, wherein said clock-selection circuit lowers a ratio of said frequency division when said input-clock signal is selected.
Claim 5
Dependent Claim
38 words
The semiconductor device as claimed in claim 3, wherein said ratio of said frequency division is lowered when said delay-control circuit sets a maximum delay amount to said variable-delay circuit so as to result in an overflow condition.
Claim 6
Dependent Claim
89 words
The semiconductor device as claimed in claim 1, wherein said clock-selection circuit compares a first timing with a second timing where a first signal indicates said first timing which is delayed behind a predetermined timing of said input-clock signal by a fixed amount of delay, and a second signal indicates said second timing which is delayed behind said predetermined timing of said input-clock signal by a delay proportional to a cycle of said input-clock signal, and selects said input-clock signal when said second timing is behind said first timing.
Claim 7
Dependent Claim
65 words
The semiconductor device as claimed in claim 5, wherein said DLL circuit further includes: a frequency divider which applies a frequency division to said input-clock signal; and a loop-control unit which controls said delay-control circuit through a feedback loop based on a signal obtained by said frequency division, wherein said clock-selection circuit lowers a ratio of said frequency division when said input-clock signal is selected.
Claim 8
Dependent Claim
38 words
The semiconductor device as claimed in claim 6, wherein said ratio of said frequency division is lowered when said delay-control circuit sets a maximum delay amount to said variable-delay circuit so as to result in an overflow condition.
Claim 9
Dependent Claim
41 words
The semiconductor device as claimed in claim 6, further comprising a fixed-delay circuit which delays a third signal by said fixed amount of delay to generate said first signal, wherein said frequency divider generates said third signal and said second signal.
Claim 10
Dependent Claim
82 words
A semiconductor device comprising: a variable-delay circuit which delays an input-clock signal to generate a delay clock signal; a DLL circuit which adjusts a clock timing; a clock-control circuit which selects one of an input-clock signal and a delayed-clock signal adjusted by said DLL circuit; and an output circuit which outputs data in synchronism with a clock signal selected by said clock-control circuit, wherein said variable-delay circuit is controlled such that said delay is not increased when said input-clock signal is selected.
Claim 11
Dependent Claim
82 words
A semiconductor device comprising: a variable-delay circuit which delays an input-clock signal to generate a delay clock signal; a DLL circuit which adjusts a clock timing; a clock-control circuit which selects one of an input-clock signal and a delayed-clock signal adjusted by said DLL circuit; and an output circuit which outputs data in synchronism with a clock signal selected by said clock-control circuit, wherein said variable-delay circuit is controlled such that said delay is not increased when said input-clock signal is selected.
Claim 12
Dependent Claim
85 words
A semiconductor device comprising: a variable-delay circuit which delays an input-clock signal to generate a delay clock signal; a clock-control circuit which selects one of the input-clock signal and the delayed clock signal; an output circuit which outputs data in synchronism with a clock signal selected by said clock-control circuit; and a DLL circuit which adjusts a delay of said variable-delay circuit, wherein said variable-delay circuit is controlled such that said delay is not increased when the input-clock signal is selected in said clock-control circuit.
Claim 13
Dependent Claim
85 words
A semiconductor device comprising: a variable-delay circuit which delays an input-clock signal to generate a delay clock signal; a clock-control circuit which selects one of the input-clock signal and the delayed clock signal; an output circuit which outputs data in synchronism with a clock signal selected by said clock-control circuit; and a DLL circuit which adjusts a delay of said variable-delay circuit, wherein said variable-delay circuit is controlled such that said delay is not increased when the input-clock signal is selected in said clock-control circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-23 | 2003-11-22 | 2004-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-23 | 2007-11-22 | 2008-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-23 | 2011-11-22 | 2012-05-23 | $7700.00 | Window Closed / Lapsed |