Patent US6693331B2 successfully refreshed from Google Patents.
US6693331B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating dual threshold voltage n-channel and p-channel MOSFETS with a single extra masked implant operation
Assignee: Intel Corp
•
Filing: 1999-11-18
•
Granted: 2004-02-17
•
Expires: 2019-11-18
Abstract
Abstract A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.
Inventors
- 👤 Kaizad R. Mistry
- 👤 Ian R. Post
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:21
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
169 words
A microelectronic device, comprising: a first NFET and a second NFET, the first NFET having a threshold voltage that is lower than the threshold voltage of the second NFET, each NFET having a channel region; a first PFET and a second PFET, the first PFET having a threshold voltage that is lower than the threshold voltage of the second PFET, each PFET having a channel region; a first NFET channel region having a first concentration of a p-type dopant and a second concentration of a p-type dopant therein; a second NFET channel region having a first concentration of a p-type dopant, a second concentration of a p-type dopant, and a third concentration of a p-type dopant therein; a second PFET channel region having a first concentration of an n-type dopant and a second concentration of an n-type dopant therein; and a first PFET channel region having a first concentration of an n-type dopant, a second concentration of an n-type dopant, and a third concentration of a p-type dopant therein.
Claim 2
Dependent Claim
169 words
A microelectronic device, comprising: a first NFET and a second NFET, the first NFET having a threshold voltage that is lower than the threshold voltage of the second NFET, each NFET having a channel region; a first PFET and a second PFET, the first PFET having a threshold voltage that is lower than the threshold voltage of the second PFET, each PFET having a channel region; a first NFET channel region having a first concentration of a p-type dopant and a second concentration of a p-type dopant therein; a second NFET channel region having a first concentration of a p-type dopant, a second concentration of a p-type dopant, and a third concentration of a p-type dopant therein; a second PFET channel region having a first concentration of an n-type dopant and a second concentration of an n-type dopant therein; and a first PFET channel region having a first concentration of an n-type dopant, a second concentration of an n-type dopant, and a third concentration of a p-type dopant therein.
Claim 3
Dependent Claim
24 words
The microelectronic device of claim 1 , wherein the p-type dopant is selected from the group consisting of boron, BF 2 , and indium.
Claim 4
Dependent Claim
22 words
The microelectronic device of claim 1 , wherein the n-type dopant is selected from the group consisting of arsenic, phosphorous, and antimony.
Claim 5
Dependent Claim
19 words
The microelectronic device of claim 1 , wherein the p-type dopant is boron, and the n-type dopant is arsenic.
Claim 6
Dependent Claim
168 words
A microelectronic device, comprising: a first NFET and a second NFET, the first NFET having a threshold voltage that is lower than the threshold voltage of the second NFET, each NFET having a channel region; a first PFET and a second PFET, the first PFET having a threshold voltage that is lower than the threshold voltage of the second PFET, each PFET having a channel region; a first NFET channel region having a first concentration of a p-type dopant, a second concentration of a p-type dopant, and a third concentration of an n-type dopant therein; a second NFET channel region having a first concentration of a p-type dopant and second concentration of a p-type dopant therein; a second PFET channel region having a first concentration of an n-type dopant, a second concentration of an n-type dopant, and a third concentration of an n-type dopant therein; and a first PFET channel region having a first concentration of an n-type dopant and a second concentration of an n-type dopant therein.
Claim 7
Dependent Claim
168 words
A microelectronic device, comprising: a first NFET and a second NFET, the first NFET having a threshold voltage that is lower than the threshold voltage of the second NFET, each NFET having a channel region; a first PFET and a second PFET, the first PFET having a threshold voltage that is lower than the threshold voltage of the second PFET, each PFET having a channel region; a first NFET channel region having a first concentration of a p-type dopant, a second concentration of a p-type dopant, and a third concentration of an n-type dopant therein; a second NFET channel region having a first concentration of a p-type dopant and second concentration of a p-type dopant therein; a second PFET channel region having a first concentration of an n-type dopant, a second concentration of an n-type dopant, and a third concentration of an n-type dopant therein; and a first PFET channel region having a first concentration of an n-type dopant and a second concentration of an n-type dopant therein.
References Cited (Backward Citations)
US4532696A
Cited
US5164805A
Cited
US5239197A
Cited
US5557231A
Cited
US5254487A
Cited
EP0614222A1
Cited
US5714796A
Cited
US5548143A
Cited
US5789788A
Cited
US5847432A
Cited
JPH08204025A
Cited
JPH0945792A
Cited
US5547894A
Cited
US6111427A
Cited
US6342719B1
Cited
GB2314974A
Cited
JPH1050860A
Cited
US5795803A
Cited
EP0849801A2
Cited
JPH114004A
Cited
US6090652A
Cited
US5952696A
Cited
US5827763A
Cited
JPH10242292A
Cited
US5963799A
Cited
US6337248B1
Cited
US6287912B1
Cited
US6462385B1
Cited
US6207510B1
Cited
US6455402B2
Cited
US6187643B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-02-16 | 2007-08-18 | 2008-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-02-16 | 2011-08-18 | 2012-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-02-16 | 2015-08-18 | 2016-02-17 | $7700.00 | Window Closed / Lapsed |