US6337248B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for manufacturing semiconductor devices
Assignee: NEC Electronics Corp
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Filing: 1999-08-19
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Granted: 2002-01-08
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Expires: 2019-08-19
Abstract
Abstract Manufactured is a semiconductor device that has a substrate and a surface channel nMOS and a buried channel nMOS as well as a surface channel pMOS and a buried channel pMOS formed on the substrate. An n + dopant is introduced prior to pattering a polycrystalline semiconductor layer that forms respective gate electrodes of the surface channel nMOS and the buried channel pMOS. A p + dopant is also introduced prior to pattering a polycrystalline semiconductor layer that forms respective gate electrodes of the surface channel pMOS and the buried channel nMOS.
Inventors
- 👤 Kiyotaka Imai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:21
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0177; H10D84/02; H10D84/03; H10D84/038; H10D30/00; H10D30/60; H10D30/637
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
150 words
A process for manufacturing a semiconductor device having a substrate and surface channel and buried channel insulated gate field effect transistors of a first conductive type and surface channel and buried channel insulated gate field effect transistors of a second conductive type formed on the substrate, comprising: forming a polycrystalline semiconductor layer on a substrate; introducing a dopant of said first conductive type prior to patterning said polycrystalline semiconductor layer forming respective gate electrodes of said surface channel insulated gate field effect transistor of said first conductive type and said buried channel insulated gate field effect transistor of said second conductive type; and introducing a dopant of said second conductive type prior to patterning said polycrystalline semiconductor layer forming respective gate electrodes of said surface channel insulated gate field effect transistor of said second conductive type and said buried channel insulated gate field effect transistor of said first conductive type.
Claim 2
Dependent Claim
150 words
A process for manufacturing a semiconductor device having a substrate and surface channel and buried channel insulated gate field effect transistors of a first conductive type and surface channel and buried channel insulated gate field effect transistors of a second conductive type formed on the substrate, comprising: forming a polycrystalline semiconductor layer on a substrate; introducing a dopant of said first conductive type prior to patterning said polycrystalline semiconductor layer forming respective gate electrodes of said surface channel insulated gate field effect transistor of said first conductive type and said buried channel insulated gate field effect transistor of said second conductive type; and introducing a dopant of said second conductive type prior to patterning said polycrystalline semiconductor layer forming respective gate electrodes of said surface channel insulated gate field effect transistor of said second conductive type and said buried channel insulated gate field effect transistor of said first conductive type.
Claim 3
Dependent Claim
19 words
The process according to claim 1 , wherein said dopant of said first conductive type is an arsenic ion.
Claim 4
Dependent Claim
19 words
The process according to claim 1 , wherein said dopant of said second conductive type is a boronic ion.
Claim 5
Dependent Claim
66 words
The process according to claim 1 , further comprising: forming said gate electrodes of said first and second conductive type; and forming a shield film on said gate electrodes to prevent implantation of dopant ions into said gate electrodes during implanting said dopant ions for forming source and drain regions of said buried channel insulated gate field effect transistors of said first and second conductive types.
Claim 6
Dependent Claim
14 words
The process according to claim 4 , wherein said shield film is a resist.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-01-07 | 2005-07-09 | 2006-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-01-07 | 2009-07-09 | 2010-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-01-07 | 2013-07-09 | 2014-01-08 | $7700.00 | Window Closed / Lapsed |