Blanket well counter doping process for high speed/low power MOSFETs

Claim 1

A method to manufacture a complementary metal oxide semiconductor device, the method comprising the steps of: providing a substrate having a P-well region and an N-well region; forming a pad oxide layer on said substrate; forming a silicon nitride pattern on said pad oxide layer to define active regions of said P-well region and an N-well region; forming a field oxide region on said substrate; removing said silicon nitride pattern; performing a first ion implantation with N-type conducting dopants on said N-well region to form an anti-punchthrough region in said N-well region; performing a second ion implantation with P-type conducting dopants on said substrate for a counter doping region of said N-well region and a doping region of said P-well region; performing a third ion implantation with P-type conducting dopants on said substrate to adjust a threshold voltage of said N-well and said P-well; performing a fourth ion implantation with N-type conducting dopants on said substrate for a counter doping region of said P-well and a doping region of said N-well region; removing said pad oxide layer; forming gate structures on said P-well region and said N-well region; and forming source/drain regions in said P-well region and said N-well region to form a NMOS device on said P-well region and a PMOS device on said N-well region.

Claim 2

A method to manufacture a complementary metal oxide semiconductor device, the method comprising the steps of: providing a substrate having a P-well region and an N-well region; forming a pad oxide layer on said substrate; forming a silicon nitride pattern on said pad oxide layer to define active regions of said P-well region and an N-well region; forming a field oxide region on said substrate; removing said silicon nitride pattern; performing a first ion implantation with N-type conducting dopants on said N-well region to form an anti-punchthrough region in said N-well region; performing a second ion implantation with P-type conducting dopants on said substrate for a counter doping region of said N-well region and a doping region of said P-well region; performing a third ion implantation with P-type conducting dopants on said substrate to adjust a threshold voltage of said N-well and said P-well; performing a fourth ion implantation with N-type conducting dopants on said substrate for a counter doping region of said P-well and a doping region of said N-well region; removing said pad oxide layer; forming gate structures on said P-well region and said N-well region; and forming source/drain regions in said P-well region and said N-well region to form a NMOS device on said P-well region and a PMOS device on said N-well region.

Claim 12

A method to manufacture a complementary metal oxide semiconductor device, the method comprising the steps of: providing a substrate having a first well region and a second well region; forming a pad oxide layer on said substrate; forming a silicon nitride pattern on said pad oxide layer to define active regions of said first well region and said second well region; forming a field oxide region on said substrate; removing said silicon nitride pattern; performing a first ion implantation with first type conducting dopants on said first well region to form an anti-punchthrough region in said first well region; performing a second ion implantation with second type conducting dopants on said substrate for a counter doping region of said first well region and a doping region of said second well region; performing a third ion implantation with second type conducting dopants on said substrate to adjust a threshold voltage of said first well region and said second well region; performing fourth ion implantation with first type conducting dopants on said substrate for a counter doping region of said second well and a doping region of said first well region; removing said pad oxide layer; forming a gate structures on said second well region and said first well region; and forming source/drain regions in said second well region and said first well region to form devices on said second well region and on said first well region.

Claim 13

A method to manufacture a complementary metal oxide semiconductor device, the method comprising the steps of: providing a substrate having a first well region and a second well region; forming a pad oxide layer on said substrate; forming a silicon nitride pattern on said pad oxide layer to define active regions of said first well region and said second well region; forming a field oxide region on said substrate; removing said silicon nitride pattern; performing a first ion implantation with first type conducting dopants on said first well region to form an anti-punchthrough region in said first well region; performing a second ion implantation with second type conducting dopants on said substrate for a counter doping region of said first well region and a doping region of said second well region; performing a third ion implantation with second type conducting dopants on said substrate to adjust a threshold voltage of said first well region and said second well region; performing fourth ion implantation with first type conducting dopants on said substrate for a counter doping region of said second well and a doping region of said first well region; removing said pad oxide layer; forming a gate structures on said second well region and said first well region; and forming source/drain regions in said second well region and said first well region to form devices on said second well region and on said first well region.