US5693505A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating a semiconductor device
Assignee: Micron Memory Japan Ltd
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Filing: 1994-12-14
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Granted: 1997-12-02
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Expires: 2014-12-14
Abstract
Abstract The invention provides a method of fabricating a semiconductor device, including the steps of forming a plurality of active regions on a semiconductor substrate, covering a first active region with mask layers including a first mask layer and a second mask layer deposited on the first mask layer, implanting first electrically conductive type impurities into a second active region with the mask layers acting as a mask, removing the second mask layer, and implanting second electrically conductive type impurities into the first and second active regions. The method makes it possible to form a retrograde-distributed tripe well with less number of masks and less number of ion implantation than conventional methods.
Inventors
- 👤 Migaku Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:12
CPC Classifications
H; H10; H10W; H10W15/00; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; H10W15/01
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
94 words
A method of fabricating a semiconductor device, comprising the steps of: forming a plurality of active regions on a semiconductor substrate; covering a first active region with mask layers including a first mask layer and a second mask layer deposited on said first mask layer; implanting first electrically conductive type impurities into second and third active regions with said mask layers acting as a mask; removing said second mask layer; covering said third active regions with a third mask layer; and implanting second electrically conductive type impurities into said first and second active regions.
Claim 2
Independent Claim
94 words
A method of fabricating a semiconductor device, comprising the steps of: forming a plurality of active regions on a semiconductor substrate; covering a first active region with mask layers including a first mask layer and a second mask layer deposited on said first mask layer; implanting first electrically conductive type impurities into second and third active regions with said mask layers acting as a mask; removing said second mask layer; covering said third active regions with a third mask layer; and implanting second electrically conductive type impurities into said first and second active regions.
Claim 3
Dependent Claim
23 words
The method as recited in claim 1, wherein said plurality of active regions are formed by oxidizing said semiconductor substrate at selected regions.
Claim 4
Dependent Claim
18 words
The method as recited in claim 1, wherein said semiconductor substrate is of a first electrically conductive type.
Claim 5
Dependent Claim
27 words
The method as recited in claim 1, wherein said first mask layer is composed of poly crystalline silicon and said second mask layer is composed of photoresist.
Claim 6
Dependent Claim
37 words
The method as recited in claim 1, wherein said step of implanting first electrically conductive type impurities and said step of implanting second electrically conductive type impurities are achieved by a plurality of ion-implantations having different ranges.
Claim 7
Dependent Claim
42 words
The method as recited in claim 1 further comprising the step of ion-implanting for adjusting a threshold voltage of a MOS type transistor, said step being carried out just before the step of covering said first active region with said mask layers.
Claim 8
Dependent Claim
45 words
The method as recited in claim 1 further comprising the step of ion-implanting for adjusting a threshold voltage of a MOS transistor, said step being carried out just before the step of implanting second electrically conductive type impurities into said first and second active regions.
Claim 9
Dependent Claim
40 words
The method as recited in claim 1 further comprising the step of covering a region located between said second and third active regions with the same mask layers as the mask layers with which said first active region is covered.
References Cited (Backward Citations)
US4717684A
Cited
US4753898A
Cited
US4908327A
Cited
US4997782A
Cited
US5460984A
Cited
US5478761A
Cited
US5342802A
Cited
US5290717A
Cited
US5091324A
Cited
US5238864A
Cited
US5278078A
Cited
US5403764A
Cited
US5254487A
Cited
US5407849A
Cited
US5396096A
Cited
US5534448A
Cited
US5498553A
Cited
US5439835A
Cited
US5432114A
Cited
US5501993A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-01 | 2001-06-02 | 2001-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-01 | 2005-06-02 | 2005-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-01 | 2009-06-02 | 2009-12-02 | $7700.00 | Window Closed / Lapsed |