US5439835A
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Process for DRAM incorporating a high-energy, oblique P-type implant for both field isolation and punchthrough
Assignee: Round Rock Research LLC
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Filing: 1994-10-14
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Granted: 1995-08-08
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Expires: 2014-10-14
Abstract
Abstract This invention is a process for fabricating a CMOS dynamic random access memory (DRAM) wherein a high-energy, oblique P-type implant is employed for punchthrough protection and field isolation enhancement or alternatively for punchthrough protection and as the sole field isolation implant. The process proceeds by forming P-type and N-type regions in a silicon substrate, performing an optional field isolation implant and forming field isolation regions using LOCOS or a modified LOCOS sequence, forming a gate dielectric layer, forming wordlines, depositing an offsetting dielectric layer, performing a low-dosage N-type implant in N-channel source/drain regions, forming spacers on the sidewalls of the gate electrodes, constructing cell capacitors superjacent the storage-node regions, performing a high-energy oblique implant with a P-type impurity which penetrates the spacers and field oxide layers, and performing a high-dosage N-type implant in bitline contact regions. As an option, the angle of the P-type oblique implant is varied through a given range to create an anti-punchthrough halo having a graded density. As a further option, a lower energy oblique implant may be performed with an N-type implant to create a graded junction for bitline junction region.
Inventors
- 👤 Fernando Gonzalez
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:14
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/222; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/0223; H10D30/0227; H10B12/30; H10B12/48; H10B12/485
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
181 words
A process for fabricating a dynamic random access memory cell array on a P-type substrate, each cell of said array having a field-effect access transistor that is insulated from neighboring access transistors by a surrounding field isolation layer, each access transistor having a first source/drain region which functions as a bitline contact region, a second source/drain region which functions as a storage node, a channel region between said first and second source/drain regions, and a gate electrode having vertical sidewalls adjacent said first and second source/drain regions, said gate electrode being dielectrically insulated from and overlying said channel region, said process comprising the following steps: (a) depositing an offsetting dielectric layer which conformally coats said vertical sidewalls; (b) performing a low-dosage N-type implant in N-channel source/drain regions; (c) constructing cell capacitors superjacent the storage-node regions; (d) forming spacers on the sidewalls of the gate electrodes; (e) performing a high-energy oblique implant with a P-type impurity which penetrates the spacers and field oxide layers; (f) performing a thermal drive-in step; and (g) performing a high-dosage N-type source/drain implant in bitline contact regions.
Claim 2
Dependent Claim
181 words
A process for fabricating a dynamic random access memory cell array on a P-type substrate, each cell of said array having a field-effect access transistor that is insulated from neighboring access transistors by a surrounding field isolation layer, each access transistor having a first source/drain region which functions as a bitline contact region, a second source/drain region which functions as a storage node, a channel region between said first and second source/drain regions, and a gate electrode having vertical sidewalls adjacent said first and second source/drain regions, said gate electrode being dielectrically insulated from and overlying said channel region, said process comprising the following steps: (a) depositing an offsetting dielectric layer which conformally coats said vertical sidewalls; (b) performing a low-dosage N-type implant in N-channel source/drain regions; (c) constructing cell capacitors superjacent the storage-node regions; (d) forming spacers on the sidewalls of the gate electrodes; (e) performing a high-energy oblique implant with a P-type impurity which penetrates the spacers and field oxide layers; (f) performing a thermal drive-in step; and (g) performing a high-dosage N-type source/drain implant in bitline contact regions.
Claim 3
Dependent Claim
16 words
The process of claim 1, wherein the impurity for the high-energy oblique P-type implant is boron.
Claim 4
Dependent Claim
30 words
The process of claim 2, wherein the high-energy oblique P-type implant is performed with an energy of 50 to 90 Kev and at a dosage level of 1E12 to 1E14.
Claim 5
Dependent Claim
30 words
The process of claim 3, wherein the high-energy oblique P-type implant is performed at an incident angle within a range of 25 to 45 degrees from normal to the substrate.
Claim 6
Dependent Claim
68 words
The process of claim 4, wherein each transistor gate comprises a portion of a wordline which traverses the array, each wordline having a pair of lateral edges, and the oblique P-type implant is performed by implanting P-type ions obliquely in two directions, each of said directions being oriented such that the P-type ions are implanted in the substrate beneath a lateral edge on each side of the wordline.
Claim 7
Dependent Claim
31 words
The process of claim 1, wherein an oblique implant is performed with an N-type impurity to create a graded junction for the bitline contact region between step (f) and step (g).
Claim 8
Dependent Claim
13 words
The process of claim 6, wherein the oblique N-type implant impurity is arsenic.
Claim 9
Dependent Claim
32 words
The process of claim 7, wherein the oblique N-type implant is performed at an energy of 80 to 120 Kev and at a dosage of within a range of 1E13 to 1E15.
Claim 10
Dependent Claim
28 words
The process of claim 8, wherein the oblique N-type implant is performed at an angle within a range of 35 to 55 degrees from normal to the substrate.
Claim 11
Dependent Claim
68 words
The process of claim 9, wherein each transistor gate comprises a portion of a wordline which traverses the array, each wordline having a pair of lateral edges, and the oblique P-type implant is performed by implanting P-type ions obliquely in two directions, each of said directions being oriented such that the P-type ions are implanted in the substrate beneath a lateral edge on each side of the wordline.
Claim 12
Dependent Claim
28 words
The process of claim 1, wherein an oblique implant is performed with an N-type impurity to create a graded junction for the bitline contact region following step (g).
Claim 13
Dependent Claim
13 words
The process of claim 11, wherein the oblique N-type implant impurity is arsenic.
Claim 14
Dependent Claim
32 words
The process of claim 12, wherein the oblique N-type implant is performed at an energy of 80 to 120 Kev and at a dosage of within a range of 1E13 to 1E15.
Claim 15
Dependent Claim
28 words
The process of claim 13, wherein the oblique N-type implant is performed at an angle within a range of 35 to 55 degrees from normal to the substrate.
Claim 16
Dependent Claim
68 words
The process of claim 14, wherein each transistor gate comprises a portion of a wordline which traverses the array, each wordline having a pair of lateral edges, and the oblique P-type implant is performed by implanting P-type ions obliquely in two directions, each of said directions being oriented such that the P-type ions are implanted in the substrate beneath a lateral edge on each side of the wordline.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-08-07 | 1999-02-06 | 1999-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-07 | 2003-02-06 | 2003-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-07 | 2007-02-06 | 2007-08-08 | $7700.00 | Window Closed / Lapsed |