Semiconductor device having stacked type capacitor

Claim 2

A semiconductor device, comprising: a capacitor upper electrode having an upper layer and a lower layer connected with each other; a capacitor lower electrode surrounding the lower layer of said capacitor upper electrode; and a capacitor insulating film interposed between said capacitor upper electrode and said capacitor lower electrode, wherein the upper layer of said capacitor upper electrode covers the upper surface and both side surfaces of said capacitor lower electrode, and the upper and lower layers of the capacitor upper electrode are electrically connected at corresponding annular portions thereof, and further wherein said capacitor lower electrode includes a first electrode layer and a second electrode layer electrically connected to each other, said first electrode layer extending under the lower layer of said capacitor upper electrode with said capacitor insulating film therebetween, and said second electrode layer extending on an upper surface of the lower layer of said capacitor upper electrode with said capacitor insulating film therebetween.

Claim 3

A semiconductor device as recited in claim 1, wherein the upper layer of said capacitor upper electrode covers the upper surface and both sidewalls of said second electrode layer and both sidewalls of said first electrode layer.

Claim 4

A semiconductor device as recited in claim 1, wherein said capacitor lower electrode includes a third electrode layer connecting the first and second electrode layers.

Claim 5

A semiconductor device as recited in claim 3, wherein said third electrode layer of the capacitor lower electrode includes an outer annular standing wall and a central standing wall formed a prescribed distance apart from the outer annular wall, and the standing walls being substantially vertical to a substrate surface, and the upper and lower layers of said capacitor upper electrode being electrically connected between said outer annular standing wall and said central standing wall at the corresponding annular portions thereof.

Claim 6

A semiconductor device, comprising a semiconductor substrate of a first type conductivity having a main surface; a pair of source/drain regions of a second type conductivity formed on the main surface of said semiconductor substrate a prescribed distance apart from each other to have therebetween a channel region; a gate electrode formed on said channel region with a gate insulating film therebetween; a capacitor lower electrode electrically connected to one of said source/drain regions; and a capacitor upper electrode formed on the surface of said capacitor lower electrode with a capacitor insulating film therebetween, said capacitor upper electrode having an upper layer and a lower layer electrically connected with each other at corresponding annular portions thereof, said capacitor lower electrode surrounding the lower layer of said capacitor upper electrode and including a first electrode layer and a second electrode layer electrically connected with each other, said first electrode layer extending on said gate electrode with an insulating film therebetween, and said second electrode layer extending on an upper surface of the lower layer of said capacitor upper electrode with said capacitor insulating film therebetween, and the upper layer of said capacitor upper electrode being formed to cover the upper surface and both side surfaces of said capacitor lower electrode.

Claim 7

A semiconductor device, comprising a semiconductor substrate of a first type conductivity having a main surface; a pair of source/drain regions of a second type conductivity formed on the main surface of said semiconductor substrate a prescribed distance apart from each other to have therebetween a channel region; a gate electrode formed on said channel region with a gate insulating film therebetween; a capacitor lower electrode electrically connected to one of said source/drain regions; and a capacitor upper electrode formed on the surface of said capacitor lower electrode with a capacitor insulating film therebetween, said capacitor upper electrode having an upper layer and a lower layer electrically connected with each other at corresponding annular portions thereof, said capacitor lower electrode surrounding the lower layer of said capacitor upper electrode and including a first electrode layer and a second electrode layer electrically connected with each other, said first electrode layer extending on said gate electrode with an insulating film therebetween, and said second electrode layer extending on an upper surface of the lower layer of said capacitor upper electrode with said capacitor insulating film therebetween, and the upper layer of said capacitor upper electrode being formed to cover the upper surface and both side surfaces of said capacitor lower electrode.

Claim 8

A semiconductor device as recited in claim 5, wherein a bit line is connected to said the other source/drain region, and said bit line is formed extending on said capacitor upper electrode with an interlayer insulating film therebetween.

Claim 9

A semiconductor device as recited in claim 6, wherein a pad layer is interposed between said bit line and said the other source/drain region, and an interlayer insulating layer is interposed between said pad layer, said capacitor upper electrode, and said capacitor lower electrode.

Claim 10

A semiconductor device as recited in claim 1, wherein said capacitor lower electrode and capacitor upper electrode are formed of polysilicon layers.

Claim 11

A semiconductor device as recited in claim 1, wherein the thickness of said capacitor lower electrode is approximately in the range between 1000 Å and 2000 Å, and the thicknesses of the upper layer and lower layer of said capacitor upper electrode are both approximately in the range between 1000 Å and 3000 Å.

Claim 12

A semiconductor device as recited in claim 5 wherein the capacitor lower electrode further includes a third electrode layer, said third electrode layer of the capacitor lower electrode includes an outer annular standing wall and a central standing wall formed a prescribed distance apart form the outer annular wall, and the standing walls being substantially vertical to a substrate surface, and the upper and lower layers of said capacitor upper electrode being electrically connected between said outer annular standing wall and said central standing wall at the corresponding annular portions thereof.