← Back to Patent Explorer
US4907046A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device with multilayer silicon oxide silicon nitride dielectric

Assignee: Micron Memory Japan Ltd
•
Filing: 1988-03-15
•
Granted: 1990-03-06
•
Expires: 2008-03-15
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A solid state device includes a transistor (A) and a capacitor (B). The capacitor is defined by a lower polycrystalline silicon layer or electrode (20), multiple dielectric layers (22), and an upper polycrystalline silicon layer or electrode (30). The dielectric layers are formed by vapor depositing a 3.6-18.6 nm thick layer of silicon nitride on the lower polycrystalline layer. Thicker silicon nitride layers increase the failure rate and decrease the capacitance (FIG. 8). More specifically, the silicon nitride layer is deposited on a thin, about 1 nm, oxidized film or surface (24) of the polycrystalline silicon layer. The silicon nitride layer is oxidized forming a silicon dioxide layer (28) until the silicon nitride layer is only about 3 nm thick. This forms on oxide layer that is 1-8.4 nm thick. If the silicon nitride layer is reduced below 3 nm, the polycrystalline silicon tends to oxidize rapidly reducing capacitance and increasing failure (FIG. 8).

Inventors

  • 👤 Yuzuru Ohji
  • 👤 Osamu Kasahara
  • 👤 Yoshitaka Tadaki
  • 👤 Hiroko Kaneko
  • 👤 Toshiyuki Mine
  • 👤 Kunihiro Yagi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 05:58
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10D; H10D1/00; H10D1/60; H10D1/68; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/6903; F; F02; F02B; F02B3/00; F02B3/06

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 156 words
A capacitor integral with a solid state device manufactured with the process of: forming a polycrystalline silicon layer with a first surface and a second surface, the first surface supported on a substrate and the second surface facing away from the substrate; allowing a natural oxide film less than 2 nm thick to form and remain on the second surface of the polycrystalline silicon layer; forming a layer of a silicon-nitrogen composition on the natural oxide film, the silicon-nitrogen composition layer being less than 18.6 nm thick and having a first face abutting the natural oxide layer and an exposed surface facing away from the natural oxide layer; oxidizing the exposed surface of the silicon-nitrogen composition layer such that at least 3 nm of the silicon-nitrogen composition remains unoxidized adjacent the natural oxide film to protect the polycrystalline silicon layer from further oxidation; and, forming an electrode layer on the oxidized silicon-nitrogen composition layer exposed surface.
Claim 2
Dependent Claim 156 words
A capacitor integral with a solid state device manufactured with the process of: forming a polycrystalline silicon layer with a first surface and a second surface, the first surface supported on a substrate and the second surface facing away from the substrate; allowing a natural oxide film less than 2 nm thick to form and remain on the second surface of the polycrystalline silicon layer; forming a layer of a silicon-nitrogen composition on the natural oxide film, the silicon-nitrogen composition layer being less than 18.6 nm thick and having a first face abutting the natural oxide layer and an exposed surface facing away from the natural oxide layer; oxidizing the exposed surface of the silicon-nitrogen composition layer such that at least 3 nm of the silicon-nitrogen composition remains unoxidized adjacent the natural oxide film to protect the polycrystalline silicon layer from further oxidation; and, forming an electrode layer on the oxidized silicon-nitrogen composition layer exposed surface.
Claim 3
Dependent Claim 117 words
A capacitor integrally constructed with a semiconductor device, the capacitor comprising: a substrate; a lower electrode including a layer of polycrystalline silicon having a first surface abutting and supported on the substrate and a thin natural oxide film of less than 2 nm formed on a second surface thereof which second surface is parallel to the first surface and faces from the supporting substrate; a multilayer dielectric including a layer of silicon-nitride disposed on the natural oxide film and a layer of silicon oxide, the silicon-nitride layer being between 3 nm and 18 nm thick and the silicon oxide layer being between 1 nm and 81/2 nm thick; and, an upper electrode mounted to the multilayer dielectric.
Claim 4
Dependent Claim 117 words
A capacitor integrally constructed with a semiconductor device, the capacitor comprising: a substrate; a lower electrode including a layer of polycrystalline silicon having a first surface abutting and supported on the substrate and a thin natural oxide film of less than 2 nm formed on a second surface thereof which second surface is parallel to the first surface and faces from the supporting substrate; a multilayer dielectric including a layer of silicon-nitride disposed on the natural oxide film and a layer of silicon oxide, the silicon-nitride layer being between 3 nm and 18 nm thick and the silicon oxide layer being between 1 nm and 81/2 nm thick; and, an upper electrode mounted to the multilayer dielectric.
Claim 5
Dependent Claim 19 words
The capacitor as set forth in claim 2 wherein the oxidized polycrystalline silicon film is about 1 nm thick.
Claim 6
Dependent Claim 18 words
The capacitor as set forth in claim 2 wherein the silicon oxide layer is about 5 nm thick.
Claim 7
Dependent Claim 35 words
The capacitor as set forth in claim 2 wherein the substrate includes at least one region doped with an impurity and wherein the polycrystalline silicon layer first surface is electrically connected with the one region.
Claim 8
Dependent Claim 171 words
A solid state device comprising: a doped substrate; first and second doped regions supported by the substrate; a gate insulated from and supported by the substrate between the first and second regions; thick insulation film covering the gate and a portion of substrate adjacent the first region; a polycrystalline silicon layer having a first surface supported by the first region and the thick insulation film and a second surface facing away from the substrate; a natural oxide film on the second surface of the polycrystalline layer; a first dielectric layer including a silicon-nitrogen composition deposited on the natural oxide film; a second dielectric layer including a silicon-oxygen composition on the first dielectric layer; the first dielectric layer having a thickness that is greater than: ##EQU7## and less than ##EQU8## where t 2 is a thickness of the second dielectric layer, t o is a thickness of the natural oxide film E SiN is a dielectric constant of the silicon-nitrogen composition, and E SiO is a dielectric constant of the silicon-oxygen composition.
Claim 9
Dependent Claim 171 words
A solid state device comprising: a doped substrate; first and second doped regions supported by the substrate; a gate insulated from and supported by the substrate between the first and second regions; thick insulation film covering the gate and a portion of substrate adjacent the first region; a polycrystalline silicon layer having a first surface supported by the first region and the thick insulation film and a second surface facing away from the substrate; a natural oxide film on the second surface of the polycrystalline layer; a first dielectric layer including a silicon-nitrogen composition deposited on the natural oxide film; a second dielectric layer including a silicon-oxygen composition on the first dielectric layer; the first dielectric layer having a thickness that is greater than: ##EQU7## and less than ##EQU8## where t 2 is a thickness of the second dielectric layer, t o is a thickness of the natural oxide film E SiN is a dielectric constant of the silicon-nitrogen composition, and E SiO is a dielectric constant of the silicon-oxygen composition.
Claim 10
Dependent Claim 31 words
The solid state device as set forth in claim 6 wherein the oxide film is less than 2 nm thick and the second dielectric layer is at least 1 nm thick.
Claim 11
Dependent Claim 28 words
The solid state device as set forth in claim 7 wherein the silicon-nitrogen composition is Si 3 N 4 and the silicon oxygen composition is SiO 2 .
Claim 12
Dependent Claim 147 words
A capacitor integrally constructed with an MOS transistor comprising: a doped substrate in which two regions doped with an n-type impurity are defined; a gate surrounded by an insulator and supported by the substrate between the two regions; a first polycrystalline silicon electrode with a natural oxide less than 1 nm thick on one surface thereof, the polycrystalline electrode having another surface in electrical communication with one of the regions and extending at least partially along the gate insulation, the first polycrystalline silicon electrode being supported by the one region and the gate electrode insulation; a multilayer dielectric including a layer of silicon-nitride disposed on the natural oxide and a layer of silicon oxide, the silicon-nitride layer being between 3 nm and 18 nm thick and the silicon oxide layer being between 1 nm and 81/2 nm thick; and, a second electrode mounted to the multilayer dielectric.
Claim 13
Dependent Claim 147 words
A capacitor integrally constructed with an MOS transistor comprising: a doped substrate in which two regions doped with an n-type impurity are defined; a gate surrounded by an insulator and supported by the substrate between the two regions; a first polycrystalline silicon electrode with a natural oxide less than 1 nm thick on one surface thereof, the polycrystalline electrode having another surface in electrical communication with one of the regions and extending at least partially along the gate insulation, the first polycrystalline silicon electrode being supported by the one region and the gate electrode insulation; a multilayer dielectric including a layer of silicon-nitride disposed on the natural oxide and a layer of silicon oxide, the silicon-nitride layer being between 3 nm and 18 nm thick and the silicon oxide layer being between 1 nm and 81/2 nm thick; and, a second electrode mounted to the multilayer dielectric.
Claim 14
Dependent Claim 133 words
A solid state device comprising: a substrate; a polycrystalline silicon layer having a first surface supported by the substrate and a second surface facing away from the substrate; a natural oxide film less than 2 nm thick on the second surface of the polycrystalline silicon layer; a silicon-nitrogen composition layer disposed on the oxide film and supported by the polycrystalline silicon layer; a silicon-oxygen composition layer disposed on and supported by the first dielectric layer; the first dielectric layer having a thickness that is greater than: ##EQU9## and less than ##EQU10## where t 2 is a thickness of the second dielectric layer, t o is a thickness of the natural oxide film, E SiN is a dielectric constant of the silicon-nitrogen composition, and E SiO is a dielectric constant of the silicon-oxygen composition.
Claim 15
Dependent Claim 133 words
A solid state device comprising: a substrate; a polycrystalline silicon layer having a first surface supported by the substrate and a second surface facing away from the substrate; a natural oxide film less than 2 nm thick on the second surface of the polycrystalline silicon layer; a silicon-nitrogen composition layer disposed on the oxide film and supported by the polycrystalline silicon layer; a silicon-oxygen composition layer disposed on and supported by the first dielectric layer; the first dielectric layer having a thickness that is greater than: ##EQU9## and less than ##EQU10## where t 2 is a thickness of the second dielectric layer, t o is a thickness of the natural oxide film, E SiN is a dielectric constant of the silicon-nitrogen composition, and E SiO is a dielectric constant of the silicon-oxygen composition.

References Cited (Backward Citations)

US4151607A Cited
US4505026A Cited
US4536947A Cited
JPS6185857A Cited
US4768080A Cited
US4805147A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-03-05 1993-09-04 1994-03-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-03-05 1997-09-04 1998-03-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-03-05 2001-09-04 2002-03-06 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag