US5245208A
Expired / Lapsed
US
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Semiconductor device and manufacturing method thereof
Assignee: Renesas Electronics Corp
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Filing: 1992-04-13
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Granted: 1993-09-14
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Expires: 2012-04-13
Abstract
Abstract A semiconductor device includes a first neutral impurity layer formed to a predetermined depth from a surface of a semiconductor substrate in a channel region that is interposed between source/drain regions and located below a gate electrode, and a second neutral impurity layer having a higher concentration than that of the first neutral impurity layer and formed to surround lower portions of the source/drain regions except for the channel region. Scattering of neutral impurities in the first neutral impurity layer suppresses generation of hot carriers, and the second neutral impurity layer suppresses diffusion of impurities in the source/drain regions in thermal processing. The second neutral impurity layer is formed by implanting neutral impurities obliquely after formation of the gate electrode.
Inventors
- 👤 Takahisa Eimori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:50
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/605; H10D30/791; H10D30/797; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/01; H10D64/021; H10P30/208; H10P30/22; H10P30/221; H10P30/222; H10P76/00; H10P76/20; H10P76/204; H10P76/2041
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
145 words
A semiconductor device, comprising: a semiconductor substrate having a main surface; a gate electrode of a predetermined width formed on said main surface with a gate insulator film therebetween; source/drain regions including a second conductivity type impurity diffusion layer, formed to extend outward from the vicinity of a portion directly beneath opposite sidewalls of said gate electrode, a channel region located below said gate electrode and interposed between said source/drain regions; a first neutral impurity layer formed to a predetermined depth from said main surface of said semiconductor substrate in said channel region and having a first concentration; and a second neutral impurity layer having a second concentration, higher than said first concentration, formed by implanting neutral impurities so as to surround a lower surface of said source/drain regions and not a lower surface of said first neutral impurity layer located below said gate electrode.
Claim 2
Dependent Claim
145 words
A semiconductor device, comprising: a semiconductor substrate having a main surface; a gate electrode of a predetermined width formed on said main surface with a gate insulator film therebetween; source/drain regions including a second conductivity type impurity diffusion layer, formed to extend outward from the vicinity of a portion directly beneath opposite sidewalls of said gate electrode, a channel region located below said gate electrode and interposed between said source/drain regions; a first neutral impurity layer formed to a predetermined depth from said main surface of said semiconductor substrate in said channel region and having a first concentration; and a second neutral impurity layer having a second concentration, higher than said first concentration, formed by implanting neutral impurities so as to surround a lower surface of said source/drain regions and not a lower surface of said first neutral impurity layer located below said gate electrode.
Claim 3
Dependent Claim
68 words
The semiconductor device according to claim 1, wherein said source/drain regions include a pair of second conductivity type impurity layers of low concentration formed to extend to a predetermined position inward from the portion directly beneath the opposite sidewalls of said gate electrode, and a pair of second conductivity type impurity layers of high concentration formed to be adjacent to said low concentration impurity layers and extend outward.
Claim 4
Dependent Claim
53 words
The semiconductor device according to claim 1, wherein said second neutral impurity layer surrounding the bottom surface of said source/drain regions comprises germanium of 10 19 -10 20 /cm 3 in concentration, and said first neutral impurity layer at said channel region comprises germanium of 10 16 -10 19 /cm 3 in concentration.
Claim 5
Dependent Claim
33 words
The semiconductor device according to claim 1, wherein a first conductivity type region of said semiconductor substrate is a p type well region, and said source/drain regions are doped with n type impurities.
Claim 6
Dependent Claim
204 words
A semiconductor device, comprising: a semiconductor substrate made of monocrystalline silicon and having a p well to a predetermined depth from a surface; a gate insulator film formed on a main surface of said semiconductor substrate; a gate insulator of a predetermined width formed on said gate insulator film; a pair of n type impurity layers of low concentration formed to extend to a predetermined position inward from a portion directly beneath opposite sidewalls of said gate electrode by implanting phosphorus; n type impurity layers of high concentration formed to be adjacent to said n type impurity layers of low concentration and extend outward by implanting arsenic; a first neutral impurity layer including germanium of 10 16 to 10 19 /cm 3 in concentration and formed to a depth of approximately 0.1 μm from said main surface of said semiconductor substrate, in a channel region that is interposed between said n type impurity layers of low concentration and located below said gate electrode; and a second neutral impurity layer including germanium of 10 19 to 10 20 /cm 3 in concentration and formed to surround lower portions of said n type impurity layers and said n type impurity layers except for said channel region.
Claim 7
Dependent Claim
204 words
A semiconductor device, comprising: a semiconductor substrate made of monocrystalline silicon and having a p well to a predetermined depth from a surface; a gate insulator film formed on a main surface of said semiconductor substrate; a gate insulator of a predetermined width formed on said gate insulator film; a pair of n type impurity layers of low concentration formed to extend to a predetermined position inward from a portion directly beneath opposite sidewalls of said gate electrode by implanting phosphorus; n type impurity layers of high concentration formed to be adjacent to said n type impurity layers of low concentration and extend outward by implanting arsenic; a first neutral impurity layer including germanium of 10 16 to 10 19 /cm 3 in concentration and formed to a depth of approximately 0.1 μm from said main surface of said semiconductor substrate, in a channel region that is interposed between said n type impurity layers of low concentration and located below said gate electrode; and a second neutral impurity layer including germanium of 10 19 to 10 20 /cm 3 in concentration and formed to surround lower portions of said n type impurity layers and said n type impurity layers except for said channel region.
References Cited (Backward Citations)
US4835112A
Cited
US5134447A
Cited
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