US5250449A
Expired / Lapsed
US
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Vertical type semiconductor device and method for producing the same
Assignee: Denso Corp
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Filing: 1991-09-30
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Granted: 1993-10-05
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Expires: 2011-09-30
Abstract
Abstract The present invention has as an object the provision of a vertical type semiconductor device whereby miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device. The line width of the gate electrode is made smaller to meet the demand for miniaturization of the cell, but the distance between the channel regions diffused into the portions below the gate at the time of double diffusion is kept to be virtually equal to that in the device of larger cell size having a low J FET resistance component. Here, the reason for making the line width of the gate electrode smaller is for securing an area for the source contact. The point is that, while the width of the gate electrode is set to be smaller, the mask members as the mask for double diffusion, having the width allowing the source region to diffuse to the portion under the gate, are attached to the side walls of the gate electrode. Thereby, miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.
Inventors
- 👤 Akira Kuroyanagi
- 👤 Masami Yamaoka
- 👤 Yoshifumi Okabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:20
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D30/0293; H10D30/60; H10D30/64; H10D30/66; H10D30/665; H10D62/00; H10D62/10; H10D62/17; H10D62/393; H10D62/102; H10D62/103; H10D62/105; H10D62/112; H10D64/00; H10D64/111; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; Y; Y10; Y10S; Y10S148/00; Y10S148/126
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
203 words
A method for producing a vertical semiconductor device comprising the steps of: preparing a semiconductor substrate provided with a semiconductor region of a first conduction type on one principal plane; forming a gate structure including at least a gate electrode on the surface of said semiconductor region; forming an insulating mask member having a width on each side of said gate structure; forming channel regions of a second conduction type, said channel regions formed from opposite sides of said gate structure in a manner self-aligning with said gate structure and said mask member to create PN junctions between said channel regions and said semiconductor region, and so that a distance L 1 between edges of said channel regions is longer than a length at which a resistance of a JFET including said channel regions below said gate structure and said semiconductor region begins increasing sharply; and forming a source region of the first conduction type in each of said channel regions in a manner self-aligning with said gate structure and said mask member to create PN junctions between said source regions and said channel regions, each of said channel regions electrically separating a corresponding one of said source regions from said semiconductor region.
Claim 2
Independent Claim
203 words
A method for producing a vertical semiconductor device comprising the steps of: preparing a semiconductor substrate provided with a semiconductor region of a first conduction type on one principal plane; forming a gate structure including at least a gate electrode on the surface of said semiconductor region; forming an insulating mask member having a width on each side of said gate structure; forming channel regions of a second conduction type, said channel regions formed from opposite sides of said gate structure in a manner self-aligning with said gate structure and said mask member to create PN junctions between said channel regions and said semiconductor region, and so that a distance L 1 between edges of said channel regions is longer than a length at which a resistance of a JFET including said channel regions below said gate structure and said semiconductor region begins increasing sharply; and forming a source region of the first conduction type in each of said channel regions in a manner self-aligning with said gate structure and said mask member to create PN junctions between said source regions and said channel regions, each of said channel regions electrically separating a corresponding one of said source regions from said semiconductor region.
Claim 3
Dependent Claim
41 words
A method for producing a vertical type semiconductor device according to claim 1, wherein said gate structure forming step includes a step for forming an auxiliary member on said gate electrode in order to control the width of said mask member.
Claim 4
Dependent Claim
27 words
A method for producing a vertical type semiconductor device according to claim 1, wherein said mask member forming step comprises a step for depositing an oxide film.
Claim 5
Dependent Claim
27 words
A method for producing a vertical type semiconductor device according to claim 1, wherein said mask member forming step comprises a step for depositing a nitride film.
Claim 6
Dependent Claim
40 words
A method for producing a vertical semiconductor device according to claim 1, wherein said step of forming said channel regions includes a step of forming said channel regions so that said distance L 1 is longer than approximately 3.5 micrometers.
Claim 7
Dependent Claim
39 words
A method for producing a vertical semiconductor device according to claim 5, wherein said step of forming said channel regions includes a step of forming said channel regions so that said distance L 1 is longer than 3.8 micrometers.
Claim 8
Dependent Claim
49 words
A method for producing a vertical semiconductor device according to claim 1, where said gate forming step includes the steps of: forming a gate electrode on said semiconductor region; oxidizing exposed surfaces of said gate electrode; and forming an oxide film over said oxidized surface of said gate electrode.
Claim 9
Dependent Claim
76 words
A method for producing a vertical semiconductor device according to claim 1, wherein said channel forming step includes the steps of: forming deep well layers of said second conductivity type on opposite sides of said gate structure; and forming regions of said second conductivity type over said deep well layers and extending more broadly and less deeply than said deep well layers, said deep well layers and said second conductivity type regions forming said channel regions.
Claim 10
Independent Claim
187 words
A method for producing a vertical power semiconductor device having a predetermined breakdown voltage, said method comprising the steps of: preparing a semiconductor substrate provided with a semiconductor region of a first conduction type on one principal plane; forming a gate structure including at least a gate electrode on a surface of said semiconductor region; forming an insulating mask member having a width on each side of said gate structure; forming channel regions of a second conduction type, said channel regions formed from opposite sides of said gate structure in a manner self-aligning with said gate structure and said mask member to create PN junctions between said channel regions and said semiconductor region, a distance L 1 between edges of said channel regions being longer than approximately 3.5 micrometers; and forming a source region of the first conductive type in each of said channel regions in a manner self-aligning with said gate structure and said mask member to create PN junctions between said source regions and said channel regions, each of said channel regions electrically separating a corresponding one of said source regions from said semiconductor region.
Claim 11
Independent Claim
187 words
A method for producing a vertical power semiconductor device having a predetermined breakdown voltage, said method comprising the steps of: preparing a semiconductor substrate provided with a semiconductor region of a first conduction type on one principal plane; forming a gate structure including at least a gate electrode on a surface of said semiconductor region; forming an insulating mask member having a width on each side of said gate structure; forming channel regions of a second conduction type, said channel regions formed from opposite sides of said gate structure in a manner self-aligning with said gate structure and said mask member to create PN junctions between said channel regions and said semiconductor region, a distance L 1 between edges of said channel regions being longer than approximately 3.5 micrometers; and forming a source region of the first conductive type in each of said channel regions in a manner self-aligning with said gate structure and said mask member to create PN junctions between said source regions and said channel regions, each of said channel regions electrically separating a corresponding one of said source regions from said semiconductor region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-10-04 | 1997-04-05 | 1997-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-04 | 2001-04-05 | 2001-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-04 | 2005-04-05 | 2005-10-05 | $7700.00 | Window Closed / Lapsed |