US5278078A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing semiconductor device
Assignee: Toshiba Corp
•
Filing: 1992-05-12
•
Granted: 1994-01-11
•
Expires: 2012-05-12
Abstract
Abstract A method of manufacturing a semiconductor device having the steps of: forming a plurality of gate electrodes on a semiconductor substrate; forming an insulating film on every second gate electrode of the plurality of gate electrodes; coating resist on the whole surface of the semiconductor device to form a first resist film; patterning the first resist film and removing a predetermined area to form a second resist film, the end face of the second resist film being aligned with the surface of the gate electrode without the insulating film; implanting impurity ions, using the second resist film as a mask, at an acceleration voltage allowing to stop the implanted ions near to the surface of the semiconductor substrate under the gate electrode with the insulating film, of those gate electrodes not covered with the second resist film; removing the second resist film and coating resist on the whole surface of the semiconductor device to form a third resist film; patterning the third resist film and removing a predetermined area to form a fourth resist film, the end face of the fourth resist film being aligned with the surface of the gate electrode with the insulating film; and implanting the impurity ions, using the fourth resist film as a mask, at an acceleration voltage allowing to stop the implanted impurity ions near at the surface of the semiconductor substrate under the gate electrode without the insulating film among the gate electrodes not covered with the fourth resist film.
Inventors
- 👤 Kazunori Kanebako
- 👤 Satoshi Inagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:00
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
236 words
A method of manufacturing a semiconductor device comprising the steps of: forming a plurality of gate electrodes on a semiconductor substrate and an insulating film on every second gate electrode of said plurality of gate electrodes; coating resist on the surface of said semiconductor device to form a first resist film; patterning said first resist film and removing a predetermined area to form a second resist film, an end face of said second resist film being aligned with the surface of a gate electrode without said insulating film; implanting impurity ions, using said second resist film as a mask, at an acceleration voltage allowing to stop said implanted ions near to the surface of said semiconductor substrate under a gate electrode with said insulating film not covered with said second resist film; removing said second resist film and coating resist on the surface of said semiconductor device to form a third resist film; patterning said third resist film and removing a predetermined area to form a fourth resist film, an end face of said fourth resist film being aligned with the surface of a gate electrode with said insulating film; and implanting impurity ions, using said fourth resist film as a mask, at an acceleration voltage allowing to stop said implanted impurity ions near to the surface of said semiconductor substrate under a gate electrode without said insulating film not covered with said fourth resist film.
Claim 2
Independent Claim
236 words
A method of manufacturing a semiconductor device comprising the steps of: forming a plurality of gate electrodes on a semiconductor substrate and an insulating film on every second gate electrode of said plurality of gate electrodes; coating resist on the surface of said semiconductor device to form a first resist film; patterning said first resist film and removing a predetermined area to form a second resist film, an end face of said second resist film being aligned with the surface of a gate electrode without said insulating film; implanting impurity ions, using said second resist film as a mask, at an acceleration voltage allowing to stop said implanted ions near to the surface of said semiconductor substrate under a gate electrode with said insulating film not covered with said second resist film; removing said second resist film and coating resist on the surface of said semiconductor device to form a third resist film; patterning said third resist film and removing a predetermined area to form a fourth resist film, an end face of said fourth resist film being aligned with the surface of a gate electrode with said insulating film; and implanting impurity ions, using said fourth resist film as a mask, at an acceleration voltage allowing to stop said implanted impurity ions near to the surface of said semiconductor substrate under a gate electrode without said insulating film not covered with said fourth resist film.
Claim 3
Independent Claim
258 words
A method of manufacturing a semiconductor device comprising the steps of: forming a plurality of gate electrodes on a semiconductor substrate and an insulating film on every second gate electrode of said plurality of gate electrodes; coating resist on the surface of said semiconductor device to form a first resist film; patterning said first resist film and removing a predetermined area to form a second resist film, an end face of said second resist film being aligned with the surface of a gate electrode without said insulating film; implanting impurity ions, using said second resist film as a mask, at an acceleration voltage allowing to stop said implanted ions near to the surface of said semiconductor substrate under a gate electrode with said insulating film not covered with said second resist film; performing a thermal diffusion process to diffuse said implanted impurity ions; removing said second resist film and coating resist on the surface of said semiconductor device to form a third resist film; patterning said third resist film and removing a predetermined area to form a fourth resist film, an end face of said fourth resist film being aligned with the surface of a gate electrode with said insulating film; implanting impurity ions, using said fourth resist film as a mask, at an acceleration voltage allowing to stop said implanted impurity ions near to the surface of said semiconductor substrate under a gate electrode without said insulating film not covered with said fourth resist film; and performing a thermal diffusion process to diffuse said implanted impurity ions.
Claim 4
Independent Claim
258 words
A method of manufacturing a semiconductor device comprising the steps of: forming a plurality of gate electrodes on a semiconductor substrate and an insulating film on every second gate electrode of said plurality of gate electrodes; coating resist on the surface of said semiconductor device to form a first resist film; patterning said first resist film and removing a predetermined area to form a second resist film, an end face of said second resist film being aligned with the surface of a gate electrode without said insulating film; implanting impurity ions, using said second resist film as a mask, at an acceleration voltage allowing to stop said implanted ions near to the surface of said semiconductor substrate under a gate electrode with said insulating film not covered with said second resist film; performing a thermal diffusion process to diffuse said implanted impurity ions; removing said second resist film and coating resist on the surface of said semiconductor device to form a third resist film; patterning said third resist film and removing a predetermined area to form a fourth resist film, an end face of said fourth resist film being aligned with the surface of a gate electrode with said insulating film; implanting impurity ions, using said fourth resist film as a mask, at an acceleration voltage allowing to stop said implanted impurity ions near to the surface of said semiconductor substrate under a gate electrode without said insulating film not covered with said fourth resist film; and performing a thermal diffusion process to diffuse said implanted impurity ions.
Claim 5
Dependent Claim
25 words
A method of manufacturing a semiconductor device according to claim 1, wherein said insulating film is a silicon oxide film or a silicon nitride film.
Claim 6
Dependent Claim
25 words
A method of manufacturing a semiconductor device according to claim 2, wherein said insulating film is a silicon oxide film or a silicon nitride film.
Claim 7
Independent Claim
261 words
A method of manufacturing a semiconductor device comprising the steps of: forming a plurality of gate electrodes on a semiconductor substrate and insulating films having a first thickness and a second thickness different from said first thickness alternately, on every second gate electrode of said plurality of gate electrodes; coating resist on the surface of said semiconductor device to form a first resist film; patterning said first resist film and removing a predetermined area to form a second resist film, an end face of said second resist film being aligned with the surface of an insulating film having said first thickness; implanting impurity ions, using said second resist film as a mask, at an acceleration voltage allowing to stop said implanted ions near to the surface of said semiconductor substrate under a gate electrode with said insulating film having said second thickness not covered with said second resist film; removing said second resist film and coating resist on the surface of said semiconductor device to form a third resist film; patterning said third resist film and removing a predetermined area to form a fourth resist film, an end face of said fourth resist film being aligned with the surface of a gate electrode with said insulating film having said second thickness; and implanting impurity ions, using said fourth resist film as a mask, at an acceleration voltage allowing to stop said implanted impurity ions near to the surface of said semiconductor substrate under a gate electrode with said insulating film having said first thickness not covered with said fourth resist film.
Claim 8
Independent Claim
261 words
A method of manufacturing a semiconductor device comprising the steps of: forming a plurality of gate electrodes on a semiconductor substrate and insulating films having a first thickness and a second thickness different from said first thickness alternately, on every second gate electrode of said plurality of gate electrodes; coating resist on the surface of said semiconductor device to form a first resist film; patterning said first resist film and removing a predetermined area to form a second resist film, an end face of said second resist film being aligned with the surface of an insulating film having said first thickness; implanting impurity ions, using said second resist film as a mask, at an acceleration voltage allowing to stop said implanted ions near to the surface of said semiconductor substrate under a gate electrode with said insulating film having said second thickness not covered with said second resist film; removing said second resist film and coating resist on the surface of said semiconductor device to form a third resist film; patterning said third resist film and removing a predetermined area to form a fourth resist film, an end face of said fourth resist film being aligned with the surface of a gate electrode with said insulating film having said second thickness; and implanting impurity ions, using said fourth resist film as a mask, at an acceleration voltage allowing to stop said implanted impurity ions near to the surface of said semiconductor substrate under a gate electrode with said insulating film having said first thickness not covered with said fourth resist film.
Claim 9
Independent Claim
283 words
A method of manufacturing a semiconductor device comprising the steps of: forming a plurality of gate electrodes on a semiconductor substrate and insulating films having a first thickness and a second thickness different from said first thickness alternately, on every second gate electrode of said plurality of gate electrodes; coating resist on the surface of said semiconductor device to form a first resist film; patterning said first resist film and removing a predetermined area to form a second resist film, an end face of said second resist film being aligned with the surface of an insulating film having said first thickness; implanting impurity ions, using said second resist film as a mask, at an acceleration voltage allowing to stop said implanted ions near to the surface of said semiconductor substrate under a gate electrode with said insulating film having said second thickness not covered with said second resist film; performing a thermal diffusion process to diffuse said implanted impurity ions; removing said second resist film and coating resist on the surface of said semiconductor device to form a third resist film; patterning said third resist film and removing a predetermined area to form a fourth resist film, an end face of said fourth resist film being aligned with the surface of a gate electrode with said insulating film having said second thickness; implanting impurity ions, using said fourth resist film as a mask, at an acceleration voltage allowing to stop said implanted impurity ions near to the surface of said semiconductor substrate under a gate electrode with said insulating film having said first thickness not covered with said fourth resist film; and performing a thermal diffusion process to diffuse said implanted impurity ions.
Claim 10
Independent Claim
283 words
A method of manufacturing a semiconductor device comprising the steps of: forming a plurality of gate electrodes on a semiconductor substrate and insulating films having a first thickness and a second thickness different from said first thickness alternately, on every second gate electrode of said plurality of gate electrodes; coating resist on the surface of said semiconductor device to form a first resist film; patterning said first resist film and removing a predetermined area to form a second resist film, an end face of said second resist film being aligned with the surface of an insulating film having said first thickness; implanting impurity ions, using said second resist film as a mask, at an acceleration voltage allowing to stop said implanted ions near to the surface of said semiconductor substrate under a gate electrode with said insulating film having said second thickness not covered with said second resist film; performing a thermal diffusion process to diffuse said implanted impurity ions; removing said second resist film and coating resist on the surface of said semiconductor device to form a third resist film; patterning said third resist film and removing a predetermined area to form a fourth resist film, an end face of said fourth resist film being aligned with the surface of a gate electrode with said insulating film having said second thickness; implanting impurity ions, using said fourth resist film as a mask, at an acceleration voltage allowing to stop said implanted impurity ions near to the surface of said semiconductor substrate under a gate electrode with said insulating film having said first thickness not covered with said fourth resist film; and performing a thermal diffusion process to diffuse said implanted impurity ions.
Claim 11
Dependent Claim
22 words
A method of manufacturing a semiconductor device according to claim 5, wherein said insulating films are silicon oxide or silicon nitride films.
Claim 12
Dependent Claim
22 words
A method of manufacturing a semiconductor device according to claim 6, wherein said insulating films are silicon oxide or silicon nitride films.
Claim 13
Dependent Claim
13 words
A method according to claim 1, wherein the impurity ions comprise boron ions.
Claim 14
Dependent Claim
15 words
A method according to claim 1, wherein the gate electrodes comprises silicide, polycide, or polysilicon.
Claim 15
Dependent Claim
20 words
A method according to claim 1, wherein the gate electrodes comprise polysilicon and the insulating films comprise silicon oxide film.
Claim 16
Dependent Claim
41 words
A method according to claim 1, wherein the steps to implant the impurity ions underneath the gate electrodes with the insulating film are performed prior to the steps to implant the impurity ions underneath the gate electrodes without the insulating film.
Claim 17
Dependent Claim
41 words
A method according to claim 1, wherein the steps to implant the impurity ions underneath the gate electrodes without the insulating film are performed prior to the steps to implant the impurity ions underneath the gate electrodes with the insulating film.
Claim 18
Dependent Claim
16 words
A method according to claim 5, wherein the first thickness is thinner than the second thickness.
Claim 19
Dependent Claim
16 words
A method according to claim 5, wherein the first thickness is thicker than the second thickness.
Claim 20
Dependent Claim
13 words
A method according to claim 5, wherein the impurity ions comprise boron ions.
Claim 21
Dependent Claim
15 words
A method according to claim 5, wherein the gate electrodes comprise silicide, polycide, or polysilicon.
Claim 22
Dependent Claim
20 words
A method according to claim 5, wherein the gate electrodes comprise polysilicon and the insulating films comprise silicon oxide film.
Claim 23
Dependent Claim
20 words
A method according to claim 2, wherein the gate electrodes comprise polysilicon and the insulating films are silicon oxide films.
Claim 24
Dependent Claim
20 words
A method according to claim 6, wherein the gate electrodes comprise polysilicon and the insulating films are silicon oxide films.
References Cited (Backward Citations)
US4364167A
Cited
US4359817A
Cited
US4364165A
Cited
US4365405A
Cited
EP0073130A2
Cited
US4818716A
Cited
US4904615A
Cited
US5028552A
Cited
US4898840A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-10 | 1997-07-12 | 1998-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-10 | 2001-07-12 | 2002-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-10 | 2005-07-12 | 2006-01-11 | $7700.00 | Window Closed / Lapsed |