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US4898840A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor integrated circuit device and a method of producing the same

Assignee: Hitachi Ltd
•
Filing: 1988-11-10
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Granted: 1990-02-06
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Expires: 2008-11-10
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Abstract

Abstract A semiconductor integrated circuit device having a read-only memory which comprises a plurality of first gate electrodes arranged on a semiconductor substrate in a first direction maintaining a predetermined distance, a plurality of second gate electrodes that are arranged among said first gate electrodes and are partly overlapped on said first gate electrodes, and regions of data-writing impurities positioned under the first and second gate electrodes. The impurities for writing data are introduced through the first or second gate electrodes using the overlappings of the first and second gate electrodes as masks.

Inventors

  • 👤 Kousuke Okuyama

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 22:57
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/0135; H10D84/0156; H10W; H10W20/00; H10W20/01

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 176 words
A method of producing semiconductor integrated circuit devices, comprising: (a) a step for introducing impurities into the surface of a semiconductor material having a first type of conductivity, said impurities having a second type of conductivity that is opposite to said first type of conductivity; (b) a step for forming a plurality of first conductive layers maintaining an equal distance on the surface of said semiconductor material; (c) a step for forming a plurality of second conductive layers among said plurality of first conductive layers on the surface of said semiconductor material, in such a manner that said second conductive layers are partly overlapped on said first conductive layers; (d) a step for forming a masking layer having openings at positions corresponding to particular ones of said plurality of first conductive layers or said plurality of second conductive layers; and (e) a step for selectively introducing impurities of the first conductivity type into the openings utilizing said masking layer; wherein said first and second conductive layers constitute gate electrodes of MISFET's that are connected in series.
Claim 2
Independent Claim 176 words
A method of producing semiconductor integrated circuit devices, comprising: (a) a step for introducing impurities into the surface of a semiconductor material having a first type of conductivity, said impurities having a second type of conductivity that is opposite to said first type of conductivity; (b) a step for forming a plurality of first conductive layers maintaining an equal distance on the surface of said semiconductor material; (c) a step for forming a plurality of second conductive layers among said plurality of first conductive layers on the surface of said semiconductor material, in such a manner that said second conductive layers are partly overlapped on said first conductive layers; (d) a step for forming a masking layer having openings at positions corresponding to particular ones of said plurality of first conductive layers or said plurality of second conductive layers; and (e) a step for selectively introducing impurities of the first conductivity type into the openings utilizing said masking layer; wherein said first and second conductive layers constitute gate electrodes of MISFET's that are connected in series.
Claim 3
Dependent Claim 56 words
A method of producing semiconductor integrated circuit devices according to claim 1, wherein said impurities having the first conductivity type are introduced through the first or the second conductive layers into the surface of said semiconductor material of the regions other than those regions where said first conductive layers and said second conductive layers are overlapped.
Claim 4
Dependent Claim 36 words
A method of producing semiconductor integrated circuit devices according to claim 2, further comprising: a step for forming a thermal oxide film on the surface of said semiconductor material prior to forming said first conductive layers.
Claim 5
Dependent Claim 40 words
A method of producing semiconductor integrated circuit devices according to claim 3, further comprising: a step for forming a thermal oxide film on the surfaces of said first conductive layers and said semiconductor material between said steps (b) and (c).
Claim 6
Dependent Claim 56 words
A method of producing semiconductor integrated circuit devices according to claim 4, further comprising: a step for introducing impurities having the second conductivity type into ends on both sides of said first and second conductive layers that are continuously formed using said first or second conductive layers as masks, after said step (c) has been finished.
Claim 7
Independent Claim 235 words
A method of producing semiconductor integrated circuit devices, comprising: (a) a step for introducing impurities into the surface of a semiconductor material having a first type of conductivity, said impurities having a second type of conductivity that is opposite to said first type of conductivity; (b) a step for forming a plurality of first conductive layers maintaining an equal distance on the surface of said semiconductor material; (c) a step for forming a plurality of second conductive layers among said plurality of first conductive layers on the surface of said semiconductor material, in such a manner that said second conductive layers are partly overlapped on said first conductive layers; (d) a step for forming a first insulating film on said semiconductor material and on the first and second conductive layers; (e) a step for selectively forming a third conductive layer on said first insulating film; (f) a step for forming a second insulating film on said first insulating film and on said third conductive layer; (g) a step for forming a masking layer on said second insulating film; (h) a step for selectively removing said masking layer using said second insulating film as an etching preventing film; and (i) a step for selectively introducing impurities of the first type of conductivity into the openings utilizing said masking layer; wherein said first and second conductive layers constitute gate electrodes of MISFET's that are connected in series.
Claim 8
Independent Claim 235 words
A method of producing semiconductor integrated circuit devices, comprising: (a) a step for introducing impurities into the surface of a semiconductor material having a first type of conductivity, said impurities having a second type of conductivity that is opposite to said first type of conductivity; (b) a step for forming a plurality of first conductive layers maintaining an equal distance on the surface of said semiconductor material; (c) a step for forming a plurality of second conductive layers among said plurality of first conductive layers on the surface of said semiconductor material, in such a manner that said second conductive layers are partly overlapped on said first conductive layers; (d) a step for forming a first insulating film on said semiconductor material and on the first and second conductive layers; (e) a step for selectively forming a third conductive layer on said first insulating film; (f) a step for forming a second insulating film on said first insulating film and on said third conductive layer; (g) a step for forming a masking layer on said second insulating film; (h) a step for selectively removing said masking layer using said second insulating film as an etching preventing film; and (i) a step for selectively introducing impurities of the first type of conductivity into the openings utilizing said masking layer; wherein said first and second conductive layers constitute gate electrodes of MISFET's that are connected in series.
Claim 9
Dependent Claim 56 words
A method of producing semiconductor integrated circuit devices according to claim 6, wherein said impurities having the first conductivity type are introduced through the first or the second conductive layers into the surface of said semiconductor material of the regions other than those regions where said first conductive layers and said second conductive layers are overlapped.
Claim 10
Dependent Claim 36 words
A method of producing semiconductor integrated circuit devices according to claim 7, further comprising: a step for forming a thermal oxide film on the surface of said semiconductor material prior to forming said first conductive layers.
Claim 11
Dependent Claim 40 words
A method of producing semiconductor integrated circuit devices according to claim 8, further comprising: a step for forming a thermal oxide film on the surfaces of said first conductive layers and said semiconductor material between said steps (b) and (c).
Claim 12
Dependent Claim 56 words
A method of producing semiconductor integrated circuit devices according to claim 9, further comprising: a step for introducing impurities having the second conductivity type into ends on both sides of said first and second conductive layers that are continuously formed using said first or second conductive layers as masks, after said step (c) has been finished.
Claim 13
Dependent Claim 38 words
A method of producing semiconductor integrated circuit devices according to claim 10, wherein the step of forming said first insulating film consists of a step of forming a silicon oxide film and a step of forming a BPSG.
Claim 14
Dependent Claim 41 words
A method of producing semiconductor integrated circuit devices according to claim 10, wherein the step of forming said third conductive layer consists of a step of forming a high-melting metal silicide layer and a step of forming an aluminum alloy layer.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-02-05 1993-08-07 1994-02-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-02-05 1997-08-07 1998-02-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-02-05 2001-08-07 2002-02-06 $7700.00 Window Closed / Lapsed

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