US4500975A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mask ROM-type semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1981-12-16
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Granted: 1985-02-19
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Expires: 2001-12-16
Abstract
Abstract A plurality of MIS-type transistors are arranged in a matrix, with each one of these MIS-type transistors corresponding to one memory information bit. These MIS-type transistors are formed so as to store and read binary information in accordance with whether the characteristic of these MIS-type transistors is normally on or normally off. At least one of the source and drain regions of the MIS-type transistors having a normally on characteristic is formed with a higher impurity density or at a greater depth compared with the regions of the MIS-type transistors having a normally off characteristic.
Inventors
- 👤 Takehide Shirato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:27
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C17/123
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
107 words
A read-only memory semiconductor device comprising: a plurality of MIS (metal insulator semiconductor)-type transistors arranged in a matrix, with each of said MIS-type transistors corresponding to one memory information bit and having a source region and a drain region, some of said MIS-type transistors having a normally on characteristic, and the remaining of said MIS-type transistors having a normally off characteristic; and at least one of said MIS-type transistors having a normally on characteristic and having a source region and a drain region with a greater depth than the depth of the source region and the drain region of said MIS transistors having a normally off characteristic.
Claim 2
Dependent Claim
107 words
A read-only memory semiconductor device comprising: a plurality of MIS (metal insulator semiconductor)-type transistors arranged in a matrix, with each of said MIS-type transistors corresponding to one memory information bit and having a source region and a drain region, some of said MIS-type transistors having a normally on characteristic, and the remaining of said MIS-type transistors having a normally off characteristic; and at least one of said MIS-type transistors having a normally on characteristic and having a source region and a drain region with a greater depth than the depth of the source region and the drain region of said MIS transistors having a normally off characteristic.
Claim 3
Dependent Claim
21 words
A read-only memory semiconductor device according to claim 1, wherein said MIS-type transistors having a normally on characteristic are punch-through transistors.
Claim 4
Dependent Claim
30 words
A read-only memory semiconductor according to claim 1, wherein the source region and the drain region of said MIS-type transistors having a normally on characteristic are connected with each other.
Claim 5
Dependent Claim
149 words
A read-only memory device operatively connectable to receive a high and a low power source voltage, comprising: a substrate; MIS (metal insulator semiconductor)-type transistors arranged in a matrix, each having a source impurity region, a drain impurity region, and a gate, said MIS-type transistors being arranged such that adjacent transistors of said MIS-type transistors arranged in the columns of said matrix are operatively connected in series between said high and low power source voltage, and adjacent transistors of said MIS-type transistors arranged in the rows of said matrix having said gates operatively connected in common; selected ones of said MIS-type transistors being normally on and the remaining of said MIS-type transistors being normally off; selected ones of said normally on MIS-type transistors having source and drain regions with a depth greater than the depth of said source and drain regions of said remaining MIS transistors having normally off characteristic.
Claim 6
Dependent Claim
149 words
A read-only memory device operatively connectable to receive a high and a low power source voltage, comprising: a substrate; MIS (metal insulator semiconductor)-type transistors arranged in a matrix, each having a source impurity region, a drain impurity region, and a gate, said MIS-type transistors being arranged such that adjacent transistors of said MIS-type transistors arranged in the columns of said matrix are operatively connected in series between said high and low power source voltage, and adjacent transistors of said MIS-type transistors arranged in the rows of said matrix having said gates operatively connected in common; selected ones of said MIS-type transistors being normally on and the remaining of said MIS-type transistors being normally off; selected ones of said normally on MIS-type transistors having source and drain regions with a depth greater than the depth of said source and drain regions of said remaining MIS transistors having normally off characteristic.
Claim 7
Dependent Claim
38 words
A read-only memory semiconductor according to claim 4, further comprising load transistors, respectively, operatively connected between said series connected MIS-type transistors and said high power source voltage, each load transistor having a gate electrode operatively connected in common.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-19 | 1988-08-20 | 1989-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-19 | 1992-08-20 | 1993-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-19 | 1996-08-20 | 1997-02-19 | $7700.00 | Window Closed / Lapsed |