Method for making an integrated circuit including high and low voltage transistors

Claim 1

A method for making an integrated circuit including high and low voltage transistors comprising: forming a plurality of spaced apart isolation regions in a substrate to define active regions therebetween; forming a first mask; using the first mask and performing at least one implant in the active regions for defining high voltage active regions for the high voltage transistors; removing the first mask and forming a second mask; using the second mask and performing only one implant for converting at least one high voltage active region into a low voltage active region for a low voltage transistor; forming gate dielectric layers on the high and low voltage active regions for corresponding high and low voltage transistors, the gate dielectric layers being formed after the high and low voltage active regions have been defined; and forming gates on the gate dielectric layers.

Claim 2

A method for making an integrated circuit including high and low voltage transistors comprising: forming a plurality of spaced apart isolation regions in a substrate to define active regions therebetween; forming a first mask; using the first mask and performing at least one implant in the active regions for defining high voltage active regions for the high voltage transistors; removing the first mask and forming a second mask; using the second mask and performing only one implant for converting at least one high voltage active region into a low voltage active region for a low voltage transistor; forming gate dielectric layers on the high and low voltage active regions for corresponding high and low voltage transistors, the gate dielectric layers being formed after the high and low voltage active regions have been defined; and forming gates on the gate dielectric layers.

Claim 12

A method for making a CMOS integrated circuit including high and low voltage transistors of a first conductivity type and high and low voltage transistors of a second conductivity type, the method comprising: forming a plurality of spaced apart isolation regions in a substrate to define active regions of a first conductivity type and active regions of a second conductivity type therebetween; forming a first mask; using the first mask and performing at least one implant in the active regions of the first conductivity type for defining high voltage active regions for the high voltage transistors of the first conductivity type; removing the first mask and forming a second mask; using the second mask and performing only one implant for converting at least one high voltage active region of the first conductivity type into a low voltage active region for a low voltage transistor of the first conductivity type; removing the second mask and forming a third mask; using the third mask and performing at least one implant in the active regions of the second conductivity type for defining high voltage active regions for the high voltage transistors of the second conductivity type; removing the third mask and forming a fourth mask; using the fourth mask and performing only one implant for converting at least one high voltage active region of the second conductivity type into a low voltage active region for a low voltage transistor of the second conductivity type; forming gate dielectric layers on the high and low voltage active regions for corresponding high and low voltage transistors of the first and second conductivity types, the gate dielectric layers being formed after the high and low voltage active regions have been defined; and forming gates on the gate dielectric layers.

Claim 13

A method for making a CMOS integrated circuit including high and low voltage transistors of a first conductivity type and high and low voltage transistors of a second conductivity type, the method comprising: forming a plurality of spaced apart isolation regions in a substrate to define active regions of a first conductivity type and active regions of a second conductivity type therebetween; forming a first mask; using the first mask and performing at least one implant in the active regions of the first conductivity type for defining high voltage active regions for the high voltage transistors of the first conductivity type; removing the first mask and forming a second mask; using the second mask and performing only one implant for converting at least one high voltage active region of the first conductivity type into a low voltage active region for a low voltage transistor of the first conductivity type; removing the second mask and forming a third mask; using the third mask and performing at least one implant in the active regions of the second conductivity type for defining high voltage active regions for the high voltage transistors of the second conductivity type; removing the third mask and forming a fourth mask; using the fourth mask and performing only one implant for converting at least one high voltage active region of the second conductivity type into a low voltage active region for a low voltage transistor of the second conductivity type; forming gate dielectric layers on the high and low voltage active regions for corresponding high and low voltage transistors of the first and second conductivity types, the gate dielectric layers being formed after the high and low voltage active regions have been defined; and forming gates on the gate dielectric layers.

Claim 27

A method for making an integrated circuit including first and second transistors respectively operating at first and second voltages, the method comprising: forming a plurality of spaced apart isolation regions in a substrate to define active regions therebetween; forming a first mask; using the first mask and performing at least one implant in the active regions for defining first active regions for the first transistors; removing the first mask and forming a second mask; using the second mask and performing only one implant for converting at least one first active region into a second active region for a second transistor; and forming gate dielectric layers on the first and second active regions for corresponding first and second transistors, the gate dielectric layers being formed after the first and second active regions have been defined.

Claim 28

A method for making an integrated circuit including first and second transistors respectively operating at first and second voltages, the method comprising: forming a plurality of spaced apart isolation regions in a substrate to define active regions therebetween; forming a first mask; using the first mask and performing at least one implant in the active regions for defining first active regions for the first transistors; removing the first mask and forming a second mask; using the second mask and performing only one implant for converting at least one first active region into a second active region for a second transistor; and forming gate dielectric layers on the first and second active regions for corresponding first and second transistors, the gate dielectric layers being formed after the first and second active regions have been defined.