US6030862A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual gate oxide formation with minimal channel dopant diffusion
Assignee: Advanced Micro Devices Inc
•
Filing: 1998-10-13
•
Granted: 2000-02-29
•
Expires: 2018-10-13
Abstract
Abstract Sharply-defined dopant profiles in the transistor channel region of ultra high density semiconductor devices are maintained by selective transistor channel implants to reduce exposure to heat cycling, thereby reducing dopant diffusion. Embodiments include forming isolation regions on a semiconductor substrate, forming a relatively thick first gate dielectric layer, then performing transistor channel implantations. The first gate dielectric layer is then masked and etched, and a second, thinner gate dielectric layer is formed. The transistor channel implants are not affected by the temperature cycle of the first gate dielectric layer formation, thereby enabling dual gate dielectric formation without adversely affecting the electrical characteristics of the finished device.
Inventors
- 👤 Nick Kepler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:41
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0181; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
181 words
A method of manufacturing a semiconductor device, which method comprises: forming a field oxide region to isolate an active area on a main surface of a semiconductor substrate; forming a first gate dielectric layer on the active area; implanting impurities into the substrate through the first gate dielectric layer; forming a mask on the first gate dielectric layer, the mask having openings over portions of the active area; etching the first gate dielectric layer to expose the portions of the active area; and forming a second gate dielectric layer on the exposed portions of the active area to a thickness less than a thickness of the first gate dielectric layer, wherein said first gate dielectric layer is formed to a first thickness in an approximately 20% oxygen atmosphere at about 800° C. to about 1000° C. for about 20 seconds to about 10 minutes and wherein said second gate dielectric layer is formed to a second thickness in an approximately 50% N 2 O atmosphere at about 800° C. to about 1000° C. for about 2 minutes to about 45 minutes.
Claim 2
Independent Claim
181 words
A method of manufacturing a semiconductor device, which method comprises: forming a field oxide region to isolate an active area on a main surface of a semiconductor substrate; forming a first gate dielectric layer on the active area; implanting impurities into the substrate through the first gate dielectric layer; forming a mask on the first gate dielectric layer, the mask having openings over portions of the active area; etching the first gate dielectric layer to expose the portions of the active area; and forming a second gate dielectric layer on the exposed portions of the active area to a thickness less than a thickness of the first gate dielectric layer, wherein said first gate dielectric layer is formed to a first thickness in an approximately 20% oxygen atmosphere at about 800° C. to about 1000° C. for about 20 seconds to about 10 minutes and wherein said second gate dielectric layer is formed to a second thickness in an approximately 50% N 2 O atmosphere at about 800° C. to about 1000° C. for about 2 minutes to about 45 minutes.
Claim 3
Dependent Claim
21 words
The method according to claim 1, comprising implanting impurities through the first gate dielectric layer to form a threshold adjust implant.
Claim 4
Dependent Claim
20 words
The method according to claim 1, comprising implanting impurities through the first gate dielectric layer to form a punch-through implant.
Claim 5
Dependent Claim
28 words
The method according to claim 1, comprising implanting impurities through the field oxide into the substrate after forming the first gate dielectric layer to form a field implant.
Claim 6
Dependent Claim
20 words
The method according to claim 1, comprising implanting impurities through the first gate dielectric layer to form a well implant.
Claim 7
Dependent Claim
48 words
The method according to claim 1, comprising: implanting impurities into the substrate prior to forming the first gate dielectric layer to form a well implant and a field implant; and implanting impurities through the first gate dielectric layer to form a punch-through implant and a threshold adjust implant.
Claim 8
Dependent Claim
50 words
The method according to claim 1, comprising: forming a photoresist mask on the first gate dielectric layer; removing the photoresist mask after etching the first gate dielectric layer; and cleaning the exposed portions of the active area and the first gate dielectric layer before forming the second gate dielectric layer.
Claim 9
Dependent Claim
13 words
The method according to claim 7, comprising cleaning by dipping in hydrofluoric acid.
Claim 10
Dependent Claim
47 words
The method according to claim 7, wherein the first gate dielectric layer has a thickness of about 60 Å to about 80 Å after the second gate dielectric is formed, and the second gate dielectric layer has a thickness of about 30 Å to about 40 Å.
Claim 11
Dependent Claim
42 words
The method according to claim 1, comprising: forming a sacrificial oxide layer on the field oxide region and the active area prior to forming the first gate dielectric layer; and removing the sacrificial oxide layer before forming the first gate dielectric layer.
Claim 12
Dependent Claim
21 words
The method according to claim 1, comprising forming the first and second gate dielectric layers of silicon dioxide by thermal oxidation.
Claim 13
Dependent Claim
17 words
The method according to claim 11, comprising forming the first gate dielectric layer in an oxygen atmosphere.
Claim 14
Dependent Claim
19 words
The method according to claim 12, comprising forming the second gate dielectric layer in an N 2 O atmosphere.
Claim 15
Dependent Claim
38 words
The method according to claim 11, comprising: forming the first gate dielectric layer to a first thickness in an oxygen atmosphere; and forming the second gate dielectric layer to a second thickness in an N 2 O atmosphere.
Claim 16
Dependent Claim
58 words
The method according to claim 11, comprising forming the first gate dielectric layer at a temperature of about 800° C. to about 1000° C. for about 2 minutes to about 45 minutes, and forming the second gate dielectric layer at a temperature of about 800° C. to about 1000° C. for about 1 minute to about 20 minutes.
Claim 17
Dependent Claim
42 words
The method according to claim 15, comprising forming the first gate dielectric layer at a temperature of about 900° C. for about 7 minutes, and forming the second gate dielectric layer at a temperature of about 900° C. for about 3 minutes.
Claim 18
Dependent Claim
58 words
The method according to claim 1, comprising: forming the second gate dielectric layer to the first thickness in an approximately 20% oxygen atmosphere at about 900° C. for about 1.5 minutes; and forming the second gate dielectric layer to the second thickness in an approximately 50% N 2 O atmosphere at about 900° C. for about 10 minutes.
Claim 19
Dependent Claim
19 words
The method according to claim 1, comprising forming the first and second gate dielectric layers by deposition silicon dioxide.
Claim 20
Dependent Claim
18 words
The method according to claim 1, comprising forming the field oxide region by one of LOCOS and STI.
Claim 21
Dependent Claim
25 words
The method according to claim 1, comprising forming the first and second gate dielectric layers of one of silicon dioxide, silicon nitride and tantalum oxide.
References Cited (Backward Citations)
US4651406A
Cited
US4554644B1
Cited
US4554644A
Cited
US5254489A
Cited
US5283200A
Cited
US5393677A
Cited
US5497021A
Cited
US5407841A
Cited
US5661045A
Cited
US5759881A
Cited
US5576226A
Cited
US5716864A
Cited
US5571745A
Cited
US5698458A
Cited
US5502009A
Cited
US5741719A
Cited
US5716863A
Cited
US5674788A
Cited
US5747368A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-28 | 2003-08-30 | 2004-02-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-28 | 2007-08-30 | 2008-02-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-28 | 2011-08-30 | 2012-02-29 | $7700.00 | Window Closed / Lapsed |