Method of fabricating memory device using a halogen implant

Claim 1

A method of fabricating a memory device, comprising the steps of: (a) forming a cell-transistor area and a peripheral area by forming a field oxidation layer over a first conductivity-type semiconductor substrate; (b) coating a photoresist film over the entire surface of the substrate; (c) exposing a surface area of the substrate by removing a portion of the photoresist film corresponding to the cell-transistor area and leaving a portion of the photoresist film corresponding to the peripheral area; (d) implanting a halogen into the exposed area of the substrate; (e) exposing the surface area of the substrate by removing the overlying photoresist film on the peripheral area; (f) after step (d), performing an oxidation to form a first gate oxidation layer over a portion of the substrate corresponding to the cell-transistor area and a second gate oxidation layer, which is thinner than the first gate oxidation layer, over a portion of the substrate corresponding to the peripheral area; (g) forming a first gate over the first gate oxidation layer and a second gate over the second gate oxidation layer by a process of deposition and then patterning of a polysilicon layer; and (h) implanting second conductivity-type ions into the substrate partly covered with the gates as a mask to form highly-doped source/drain areas in the respective cell-transistor and peripheral areas, thereby forming respective MOS transistors on each of the cell-transistor area and the peripheral area.

Claim 2

A method of fabricating a memory device, comprising the steps of: (a) forming a cell-transistor area and a peripheral area by forming a field oxidation layer over a first conductivity-type semiconductor substrate; (b) coating a photoresist film over the entire surface of the substrate; (c) exposing a surface area of the substrate by removing a portion of the photoresist film corresponding to the cell-transistor area and leaving a portion of the photoresist film corresponding to the peripheral area; (d) implanting a halogen into the exposed area of the substrate; (e) exposing the surface area of the substrate by removing the overlying photoresist film on the peripheral area; (f) after step (d), performing an oxidation to form a first gate oxidation layer over a portion of the substrate corresponding to the cell-transistor area and a second gate oxidation layer, which is thinner than the first gate oxidation layer, over a portion of the substrate corresponding to the peripheral area; (g) forming a first gate over the first gate oxidation layer and a second gate over the second gate oxidation layer by a process of deposition and then patterning of a polysilicon layer; and (h) implanting second conductivity-type ions into the substrate partly covered with the gates as a mask to form highly-doped source/drain areas in the respective cell-transistor and peripheral areas, thereby forming respective MOS transistors on each of the cell-transistor area and the peripheral area.