Method of manufacturing a semiconductor device

Claim 3

A method as claimed in claim 1, characterized in that said masking layer comprises a thermal oxide layer on the silicon layer and a silicon nitride layer on said thermal oxide layer.

Claim 4

A method as claimed in claim 1 or 2, characterized in that at a location other than that of the field effect transistor said masking layer is covered with a conductive layer which together with the underlying silicon layer forms the plates of a voltage-independent capacitor, said masking layer forming the dielectric of said capacitor.

Claim 6

A method as claimed in claim 2, characterized in that the thickness of said thermal oxide layer is at most 20 nm, that of said silicon nitride layer is at most 60 nm and that of said silicon layer is at most 350 nm.

Claim 7

A method as claimed in claim 1 or 2, characterized in that the nitrogen ion implantation is carried out with a dose of at least 2×10 15 ions/cm 2 and at most 3×10 15 ions/cm 2 .

Claim 8

A method as claimed in claim 1 or 2, characterized in that after the formation of the source and drain zones a further insulating layer is provided on the surface, after which contact windows are etched in said further insulating layer.

Claim 9

A method as claimed in claim 7, characterized in that before providing the further insulating layer said masking layer is locally removed from the silicon pattern.

Claim 10

A method as claimed in claim 1 or 2, characterized in that two complementary insulated gate field effect transistors are manufactured in which around each of the transistors an at least partly countersunk oxide pattern is formed and in which the first transistor is provided in a substrate region of a first conductivity type and the second transistor is formed in a region of the second, opposite conductivity type which within the semiconductor body is surrounded entirely by the substrate region and forms therewith a p-n junction terminating at the oxide pattern.

Claim 11

A method as claimed in claim 9, characterized in that the starting material is an n-type silicon substrate, that an antioxidation mask is provided on the surface at the area where the field effect transistor is to be formed, that the non-masked surface regions are then exposed to a phosphorus ion implantation and are then thermally oxidized to form a partly countersunk oxide pattern, that an etching mask is then provided which at the area of the first transistor does not cover the antioxidation mask and an edge region of the oxide patern situated therearound, that the uncovered part of the oxide pattern is then removed by etching and a first boron implantation is carried out through the anti-oxidation mask and into the region not covered by the etching mask, and, after removing the etching mask, the boron atoms are further indiffused, after which a second boron implantation with a higher dosage and lower energy then the first boron implantation is carried out in the region not covered by the anti-oxidation mask and the oxide pattern, that the oxide pattern is then completed by means of a further thermal oxidation, after which the surface regions present below the anti-oxidation mask are exposed and the field effect transistors are provided in said regions.