Simplified semiconductor device manufacturing using low energy high tilt angle and high energy post-gate ion implantation (PoGI)

Claim 1

A method for use in the fabrication of a circuit on a substrate, comprising the steps of: after formation of gate electrodes, depositing a sidewall insulator layer and etching the sidewall insulator layer to form sidewall spacers on the sides of the gate electrodes; implanting source/drain extensions of p-type devices through openings in a first mask; implanting source/drain regions of the p-type devices through the openings in said first mask; implanting source/drain extensions of n-type devices through openings in a second mask; implanting source/drain regions of the n-type devices through the openings in said second mask, the steps of implanting source/drain extensions being performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein said source/drain extensions are formed laterally under said sidewall spacers, and the steps of implanting source/drain regions being performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the steps of implanting source/drain extensions; and implanting an n-well for the p-type devices through the openings in said first mask, implanting a channel stop for the p-type devices through the openings in said first mask, and implanting a V tp threshold adjust for the p-type devices through the openings in said first mask, the steps of implanting said n-well, said channel stop and said V tp threshold adjust for the p-type devices being performed at sufficient energy to pass through said gate electrodes and at low or zero tilt angle with respect to the normal to the substrate surface.

Claim 2

A method for use in the fabrication of a circuit on a substrate, comprising the steps of: after formation of gate electrodes, depositing a sidewall insulator layer and etching the sidewall insulator layer to form sidewall spacers on the sides of the gate electrodes; implanting source/drain extensions of p-type devices through openings in a first mask; implanting source/drain regions of the p-type devices through the openings in said first mask; implanting source/drain extensions of n-type devices through openings in a second mask; implanting source/drain regions of the n-type devices through the openings in said second mask, the steps of implanting source/drain extensions being performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein said source/drain extensions are formed laterally under said sidewall spacers, and the steps of implanting source/drain regions being performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the steps of implanting source/drain extensions; and implanting an n-well for the p-type devices through the openings in said first mask, implanting a channel stop for the p-type devices through the openings in said first mask, and implanting a V tp threshold adjust for the p-type devices through the openings in said first mask, the steps of implanting said n-well, said channel stop and said V tp threshold adjust for the p-type devices being performed at sufficient energy to pass through said gate electrodes and at low or zero tilt angle with respect to the normal to the substrate surface.

Claim 12

A method for use in the fabrication of a device on a substrate, comprising the steps of: after formation of a gate electrode of the device, depositing a sidewall insulator layer and etching the sidewall insulator layer to form sidewall spacers on the sides of the gate electrode; implanting source/drain extensions of the device through openings in a mask, the step of implanting source/drain extensions being performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein said source/drain extensions are formed laterally under said sidewall spacers; implanting source/drain regions of the device through the openings in said mask, the step of implanting source/drain regions being performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the step of implanting source/drain extensions; and implanting a well for the device through the openings in said mask, implanting a channel stop for the device through the openings in said mask and implanting a V t threshold adjust for the device through the openings in said mask, the steps of implanting said well, said channel stop and said V t threshold adjust being performed at sufficient energy to pass through said gate electrode and at low or zero tilt angle with respect to the normal to the substrate surface.

Claim 13

A method for use in the fabrication of a device on a substrate, comprising the steps of: after formation of a gate electrode of the device, depositing a sidewall insulator layer and etching the sidewall insulator layer to form sidewall spacers on the sides of the gate electrode; implanting source/drain extensions of the device through openings in a mask, the step of implanting source/drain extensions being performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein said source/drain extensions are formed laterally under said sidewall spacers; implanting source/drain regions of the device through the openings in said mask, the step of implanting source/drain regions being performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the step of implanting source/drain extensions; and implanting a well for the device through the openings in said mask, implanting a channel stop for the device through the openings in said mask and implanting a V t threshold adjust for the device through the openings in said mask, the steps of implanting said well, said channel stop and said V t threshold adjust being performed at sufficient energy to pass through said gate electrode and at low or zero tilt angle with respect to the normal to the substrate surface.

Claim 18

A method for use in the fabrication of a circuit on a substrate, comprising the steps of: after formation of gate electrodes, depositing a sidewall insulator layer and etching the sidewall insulator layer to form sidewall spacers on the sides of the gate electrodes; implanting source/drain extensions of p-type devices through openings in a first mask; implanting source/drain regions of the p-type devices through the openings in said first mask; implanting source/drain extensions of n-type devices through openings in a second mask; implanting source/drain regions of the n-type devices through the openings in said second mask, the steps of implanting source/drain extensions being performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein said source/drain extensions are formed laterally under said sidewall spacers, and the steps of implanting source/drain regions being performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the steps of implanting source/drain extensions; and implanting a p-well for the n-type devices through the openings in said second mask, implanting a channel stop for the n-type devices through the openings in said second mask, and implanting a V tn threshold adjust for the n-type devices through the openings in said second mask, the steps of implanting said p-well, said channel stop and said V tn threshold adjust for the n-type devices being performed at sufficient energy to pass through said gate electrodes and at low or zero tilt angle with respect to the normal to the substrate surface.

Claim 19

A method for use in the fabrication of a circuit on a substrate, comprising the steps of: after formation of gate electrodes, depositing a sidewall insulator layer and etching the sidewall insulator layer to form sidewall spacers on the sides of the gate electrodes; implanting source/drain extensions of p-type devices through openings in a first mask; implanting source/drain regions of the p-type devices through the openings in said first mask; implanting source/drain extensions of n-type devices through openings in a second mask; implanting source/drain regions of the n-type devices through the openings in said second mask, the steps of implanting source/drain extensions being performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein said source/drain extensions are formed laterally under said sidewall spacers, and the steps of implanting source/drain regions being performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the steps of implanting source/drain extensions; and implanting a p-well for the n-type devices through the openings in said second mask, implanting a channel stop for the n-type devices through the openings in said second mask, and implanting a V tn threshold adjust for the n-type devices through the openings in said second mask, the steps of implanting said p-well, said channel stop and said V tn threshold adjust for the n-type devices being performed at sufficient energy to pass through said gate electrodes and at low or zero tilt angle with respect to the normal to the substrate surface.