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Patent US6187643B1 successfully refreshed from Google Patents.
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US6187643B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Simplified semiconductor device manufacturing using low energy high tilt angle and high energy post-gate ion implantation (PoGI)

Assignee: Varian Semiconductor Equipment Associates Inc
•
Filing: 1999-06-29
•
Granted: 2001-02-13
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Expires: 2019-06-29
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Abstract

Abstract Methods are provided for fabrication of a circuit on a substrate. After formation of gate electrodes, sidewall spacers are formed on the sides of the gate electrodes. Source/drain extensions and source/drain regions of p-type devices are implanted through openings in a first mask. Source/drain extensions and source/drain regions of n-type devices are implanted through openings in a second mask. The source/drain extensions are implanted at low energy and at a high tilt angle with respect to a normal to the substrate surface, so that the source/drain extensions are formed laterally under the sidewall spacers. The source/drain regions are implanted at low or zero tilt angle and at equal to or higher energy and higher dose than the steps of implanting the source/drain extensions. In one optional feature, the first and second masks are used for implanting wells, channel stops and threshold adjusts for the p-type devices and the n-type devices, respectively. In another optional feature, a third mask is used to perform a buried implanted layer for lateral isolation (BILLI) process.

Inventors

  • 👤 John O. Borland

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 20:42
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0217; H10P; H10P30/00; H10P30/20; H10D30/0223; H10D30/0227; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10P30/22; H10P30/221; H10P30/222; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/0127; H10W10/014; H10W10/0148; H10W10/10; H10W10/13; H10W10/17

Claims Analysis

Total Claims: 19
Claim 1
Independent Claim 268 words
A method for use in the fabrication of a circuit on a substrate, comprising the steps of: after formation of gate electrodes, depositing a sidewall insulator layer and etching the sidewall insulator layer to form sidewall spacers on the sides of the gate electrodes; implanting source/drain extensions of p-type devices through openings in a first mask; implanting source/drain regions of the p-type devices through the openings in said first mask; implanting source/drain extensions of n-type devices through openings in a second mask; implanting source/drain regions of the n-type devices through the openings in said second mask, the steps of implanting source/drain extensions being performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein said source/drain extensions are formed laterally under said sidewall spacers, and the steps of implanting source/drain regions being performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the steps of implanting source/drain extensions; and implanting an n-well for the p-type devices through the openings in said first mask, implanting a channel stop for the p-type devices through the openings in said first mask, and implanting a V tp threshold adjust for the p-type devices through the openings in said first mask, the steps of implanting said n-well, said channel stop and said V tp threshold adjust for the p-type devices being performed at sufficient energy to pass through said gate electrodes and at low or zero tilt angle with respect to the normal to the substrate surface.
Claim 2
Independent Claim 268 words
A method for use in the fabrication of a circuit on a substrate, comprising the steps of: after formation of gate electrodes, depositing a sidewall insulator layer and etching the sidewall insulator layer to form sidewall spacers on the sides of the gate electrodes; implanting source/drain extensions of p-type devices through openings in a first mask; implanting source/drain regions of the p-type devices through the openings in said first mask; implanting source/drain extensions of n-type devices through openings in a second mask; implanting source/drain regions of the n-type devices through the openings in said second mask, the steps of implanting source/drain extensions being performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein said source/drain extensions are formed laterally under said sidewall spacers, and the steps of implanting source/drain regions being performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the steps of implanting source/drain extensions; and implanting an n-well for the p-type devices through the openings in said first mask, implanting a channel stop for the p-type devices through the openings in said first mask, and implanting a V tp threshold adjust for the p-type devices through the openings in said first mask, the steps of implanting said n-well, said channel stop and said V tp threshold adjust for the p-type devices being performed at sufficient energy to pass through said gate electrodes and at low or zero tilt angle with respect to the normal to the substrate surface.
Claim 3
Dependent Claim 27 words
A method as defined in claim 1 further comprising the step of performing a halo implant of the p-type devices through the openings in said first mask.
Claim 4
Dependent Claim 27 words
A method as defined in claim 1 further comprising the step of performing a halo implant of the n-type devices through the openings in said second mask.
Claim 5
Dependent Claim 28 words
A method as defined in claim 1 wherein the steps of implanting source/drain extensions are performed at tilt angles in a range of about 45 to 60 degrees.
Claim 6
Dependent Claim 28 words
A method as defined in claim 1 further comprising the step of implanting a pre-amorphization layer prior to the steps of implanting source/drain extensions and implanting source/drain regions.
Claim 7
Dependent Claim 31 words
A method as defined in claim 5 further comprising the step of thermally treating the substrate at 500° C. to 800° C. in a low temperature solid phase epitaxial regrowth process.
Claim 8
Dependent Claim 36 words
A method as defined in claim 1 wherein the steps of implanting source/drain extensions are performed at tilt angles and energies selected such that the source/drain extensions are formed laterally under portions of said gate electrodes.
Claim 9
Dependent Claim 27 words
A method as defined in claim 1 further comprising the step of implanting a punchthrough stop for the p-type devices through the openings in said first mask.
Claim 10
Dependent Claim 105 words
A method as defined in claim 1 further comprising the steps of implanting a p-well for the n-type devices through the openings in said second mask, implanting a channel stop for the n-type devices through the openings in said second mask, and implanting a V tn threshold adjust for the n-type devices through the openings in said second mask, the steps of implanting said p-well, said channel stop and said V tn threshold adjust for the n-type devices being performed at sufficient energy to pass through said gate electrodes and at low or zero tilt angle with respect to the normal to the substrate surface.
Claim 11
Dependent Claim 27 words
A method as defined in claim 9 further comprising the step of implanting a punchthrough stop for the n-type devices through the openings in said second mask.
Claim 12
Independent Claim 232 words
A method for use in the fabrication of a device on a substrate, comprising the steps of: after formation of a gate electrode of the device, depositing a sidewall insulator layer and etching the sidewall insulator layer to form sidewall spacers on the sides of the gate electrode; implanting source/drain extensions of the device through openings in a mask, the step of implanting source/drain extensions being performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein said source/drain extensions are formed laterally under said sidewall spacers; implanting source/drain regions of the device through the openings in said mask, the step of implanting source/drain regions being performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the step of implanting source/drain extensions; and implanting a well for the device through the openings in said mask, implanting a channel stop for the device through the openings in said mask and implanting a V t threshold adjust for the device through the openings in said mask, the steps of implanting said well, said channel stop and said V t threshold adjust being performed at sufficient energy to pass through said gate electrode and at low or zero tilt angle with respect to the normal to the substrate surface.
Claim 13
Independent Claim 232 words
A method for use in the fabrication of a device on a substrate, comprising the steps of: after formation of a gate electrode of the device, depositing a sidewall insulator layer and etching the sidewall insulator layer to form sidewall spacers on the sides of the gate electrode; implanting source/drain extensions of the device through openings in a mask, the step of implanting source/drain extensions being performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein said source/drain extensions are formed laterally under said sidewall spacers; implanting source/drain regions of the device through the openings in said mask, the step of implanting source/drain regions being performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the step of implanting source/drain extensions; and implanting a well for the device through the openings in said mask, implanting a channel stop for the device through the openings in said mask and implanting a V t threshold adjust for the device through the openings in said mask, the steps of implanting said well, said channel stop and said V t threshold adjust being performed at sufficient energy to pass through said gate electrode and at low or zero tilt angle with respect to the normal to the substrate surface.
Claim 14
Dependent Claim 29 words
A method as defined in claim 11 wherein the step of implanting source/drain extensions is performed at a tilt angle in a range of about 45 to 60 degrees.
Claim 15
Dependent Claim 28 words
A method as defined in claim 11 further comprising the step of implanting a pre-amorphization layer prior to the steps of implanting source/drain extensions and implanting source/drain regions.
Claim 16
Dependent Claim 31 words
A method as defined in claim 13 further comprising the step of thermally treating the substrate at 500° C. to 800° C. in a low temperature solid phase epitaxial regrowth process.
Claim 17
Dependent Claim 36 words
A method as defined in claim 11 wherein the steps of implanting source/drain extensions are performed at tilt angles and energies selected such that the source/drain extensions are formed laterally under portions of said gate electrodes.
Claim 18
Independent Claim 268 words
A method for use in the fabrication of a circuit on a substrate, comprising the steps of: after formation of gate electrodes, depositing a sidewall insulator layer and etching the sidewall insulator layer to form sidewall spacers on the sides of the gate electrodes; implanting source/drain extensions of p-type devices through openings in a first mask; implanting source/drain regions of the p-type devices through the openings in said first mask; implanting source/drain extensions of n-type devices through openings in a second mask; implanting source/drain regions of the n-type devices through the openings in said second mask, the steps of implanting source/drain extensions being performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein said source/drain extensions are formed laterally under said sidewall spacers, and the steps of implanting source/drain regions being performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the steps of implanting source/drain extensions; and implanting a p-well for the n-type devices through the openings in said second mask, implanting a channel stop for the n-type devices through the openings in said second mask, and implanting a V tn threshold adjust for the n-type devices through the openings in said second mask, the steps of implanting said p-well, said channel stop and said V tn threshold adjust for the n-type devices being performed at sufficient energy to pass through said gate electrodes and at low or zero tilt angle with respect to the normal to the substrate surface.
Claim 19
Independent Claim 268 words
A method for use in the fabrication of a circuit on a substrate, comprising the steps of: after formation of gate electrodes, depositing a sidewall insulator layer and etching the sidewall insulator layer to form sidewall spacers on the sides of the gate electrodes; implanting source/drain extensions of p-type devices through openings in a first mask; implanting source/drain regions of the p-type devices through the openings in said first mask; implanting source/drain extensions of n-type devices through openings in a second mask; implanting source/drain regions of the n-type devices through the openings in said second mask, the steps of implanting source/drain extensions being performed at low energy and at a high tilt angle with respect to a normal to the substrate surface, wherein said source/drain extensions are formed laterally under said sidewall spacers, and the steps of implanting source/drain regions being performed at low or zero tilt angle with respect to the normal to the substrate surface and at equal to or higher energy and higher dose than the steps of implanting source/drain extensions; and implanting a p-well for the n-type devices through the openings in said second mask, implanting a channel stop for the n-type devices through the openings in said second mask, and implanting a V tn threshold adjust for the n-type devices through the openings in said second mask, the steps of implanting said p-well, said channel stop and said V tn threshold adjust for the n-type devices being performed at sufficient energy to pass through said gate electrodes and at low or zero tilt angle with respect to the normal to the substrate surface.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-02-13 2004-08-14 2005-02-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-02-13 2008-08-14 2009-02-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-02-13 2012-08-14 2013-02-13 $7700.00 Window Closed / Lapsed

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