Method of making a self-aligned silicide

Claim 1

A method of manufacturing a self-aligned silicide, comprising: providing a first conductivity type substrate having at least a MOS component region thereabove, with the MOS component region including a gate region, lightly doped regions and isolating regions; depositing a first insulating layer above a surface of the substrate; anisotropic overetching the first insulating layer to remove the first insulating layer and form spacers on a respective sidewalls of the gate region, and to simultaneously remove a portion of an upper layer of the isolating regions; implanting second conductivity type ions at a tilt angle into the MOS component region while spinning the substrate, using the spacers and gate region as masks, to form a plurality of source/drain regions in the substrate on each side of the gate region, each source/drain region being formed with a second conductivity type impurity diffusion region located immediately adjacent to a respective one of the isolating regions and having a junction depth that is greater than a depth of all other portions of the respective source/drain region; forming a metallic layer over a surface of the substrate, the MOS component region and spacers; performing rapid thermal processing to cause the metallic layer to react with a silicon on a top surface of the gate region and the source/drain regions and form a metal silicide layer; subsequent to said performing, selectively etching to remove any unreacted portion of the metallic layer;. sequentially forming a second insulating layer and a dielectric layer above a surface of the substrate, the MOS component region, the spacers and the metal silicide layer; patterning the dielectric layer, using the second insulating layer as an etching stop, to form a plurality of wide border contact windows; and removing the second insulating layer through the wide border contact windows so as to expose the metal silicide layer.

Claim 2

A method of manufacturing a self-aligned silicide, comprising: providing a first conductivity type substrate having at least a MOS component region thereabove, with the MOS component region including a gate region, lightly doped regions and isolating regions; depositing a first insulating layer above a surface of the substrate; anisotropic overetching the first insulating layer to remove the first insulating layer and form spacers on a respective sidewalls of the gate region, and to simultaneously remove a portion of an upper layer of the isolating regions; implanting second conductivity type ions at a tilt angle into the MOS component region while spinning the substrate, using the spacers and gate region as masks, to form a plurality of source/drain regions in the substrate on each side of the gate region, each source/drain region being formed with a second conductivity type impurity diffusion region located immediately adjacent to a respective one of the isolating regions and having a junction depth that is greater than a depth of all other portions of the respective source/drain region; forming a metallic layer over a surface of the substrate, the MOS component region and spacers; performing rapid thermal processing to cause the metallic layer to react with a silicon on a top surface of the gate region and the source/drain regions and form a metal silicide layer; subsequent to said performing, selectively etching to remove any unreacted portion of the metallic layer;. sequentially forming a second insulating layer and a dielectric layer above a surface of the substrate, the MOS component region, the spacers and the metal silicide layer; patterning the dielectric layer, using the second insulating layer as an etching stop, to form a plurality of wide border contact windows; and removing the second insulating layer through the wide border contact windows so as to expose the metal silicide layer.