US5686324A
Expired / Lapsed
US
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Process for forming LDD CMOS using large-tilt-angle ion implantation
Assignee: Promos Technologies Inc
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Filing: 1996-03-28
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Granted: 1997-11-11
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Expires: 2016-03-28
Abstract
Abstract A method and resulting integrated circuit device, and in particular a CMOS integrated circuit device, having a fabrication method and structure therefor for an improved lightly doped drain region. The method includes the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectic over each P type well and N type well regions. The method then performs a blanket N type implant step at an angle being about 45° or greater from a perpendicular to the gate electrodes in both the P type and N type well regions. The blanket N type implant forms an LDD region in the P type well region. Sidewall spacers are then formed on edges of the gate electrodes. The method then performs two separate N type implants into the P type well region, each at different angles and dosages to form the N type LDD source/drain region for an NMOS device. The method also performs two separate P type implants into the N type well region, each at different angles and dosages to form the P type LDD source/drain region for a PMOS device. The present LDD fabrication method provides a relatively consistent and easy to fabricate CMOS LDD region, with less masking steps and improved device performance.
Inventors
- 👤 Chih-Hsien Wang
- 👤 Min-Liang Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:59
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/605; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10P; H10P30/00; H10P30/20; H10P30/222
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
243 words
A method of fabricating a CMOS integrated circuit device, said method comprising: providing a semiconductor substrate, said semiconductor substrate comprising a first well region of a first conductivity type and a second well region of a second conductivity type, said first well region having a first gate electrode overlying a first gate dielectric layer, said second well region having a second gate electrode overlying a second gate dielectric layer; blanketly introducing a first impurity of said second conductivity type into said first well region and said second well region, said first impurity in said first well region defining a first LDD region; forming first sidewall spacers on edges of said first gate electrode and second sidewall spacers on edges of said second gate electrode; introducing a second impurity of said second conductivity type into said first well region and introducing a third impurity of said second conductivity type into said first well region said second impurity in said first well region defining a first dose of a first source/drain region, said third impurity in said first well region defining a second dose of said first source/drain region; and introducing a fourth impurity of said first conductivity type into said second well region and introducing a fifth impurity of said first conductivity type into said second well region, said fourth impurity in said second well region defining a second LDD region, said fifth impurity in said second well region defining a second source/drain region.
Claim 2
Independent Claim
243 words
A method of fabricating a CMOS integrated circuit device, said method comprising: providing a semiconductor substrate, said semiconductor substrate comprising a first well region of a first conductivity type and a second well region of a second conductivity type, said first well region having a first gate electrode overlying a first gate dielectric layer, said second well region having a second gate electrode overlying a second gate dielectric layer; blanketly introducing a first impurity of said second conductivity type into said first well region and said second well region, said first impurity in said first well region defining a first LDD region; forming first sidewall spacers on edges of said first gate electrode and second sidewall spacers on edges of said second gate electrode; introducing a second impurity of said second conductivity type into said first well region and introducing a third impurity of said second conductivity type into said first well region said second impurity in said first well region defining a first dose of a first source/drain region, said third impurity in said first well region defining a second dose of said first source/drain region; and introducing a fourth impurity of said first conductivity type into said second well region and introducing a fifth impurity of said first conductivity type into said second well region, said fourth impurity in said second well region defining a second LDD region, said fifth impurity in said second well region defining a second source/drain region.
Claim 3
Dependent Claim
14 words
The method of claim 1 wherein said first conductivity type is a P type.
Claim 4
Dependent Claim
14 words
The method of claim 1 wherein said second conductivity type is an N type.
Claim 5
Dependent Claim
13 words
The method of claim 1 wherein said first impurity is an N- type.
Claim 6
Dependent Claim
28 words
The method of claim 1 wherein said first impurity is an N- type, said second impurity is an N+ type, and said third impurity is an N++ type.
Claim 7
Dependent Claim
12 words
The method of claim 5 wherein said first impurity is angle implanted.
Claim 8
Dependent Claim
12 words
The method of claim 5 wherein said second impurity is angle implanted.
Claim 9
Dependent Claim
42 words
The method of claim 1 wherein said first impurity is an N- type, said second impurity is an N+ type, said third impurity is an N++ type, said fourth impurity is a P- type, and said fifth impurity is a P++ type.
Claim 10
Dependent Claim
12 words
The method of claim 8 wherein said fourth impurity is angle implanted.
Claim 11
Dependent Claim
25 words
The method of claim 1 wherein each of said first sidewall spacers is provided with a width ranging from about 0.2 to about 0.4 microns.
Claim 12
Dependent Claim
25 words
The method of claim 1 wherein each of said second sidewall spacers is provided with a width ranging from about 0.2 to about 0.4 microns.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-11-10 | 2001-05-12 | 2001-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-10 | 2005-05-12 | 2005-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-10 | 2009-05-12 | 2009-11-11 | $7700.00 | Window Closed / Lapsed |