Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation

Claim 1

A method of forming a complementary metal oxide semiconductor (CMOS) integrated circuit device, said method comprising: providing a semiconductor substrate comprising a P type well region and a N type well region, a first gate dielectric layer overlying said P type well region and a second gate dielectric layer overlying said N type well region, a first gate electrode overlying said first gate dielectric layer and a second gate electrode overlying said second gate dielectric layer; introducing a N impurity type at a first concentration into said P type well region and introducing a P impurity type at a second concentration into said N type well region, said N impurity type in said P type well region defining a first LDD region and said P impurity type in said N type well region defining a second LDD region; forming first sidewall spacers on edges of said first gate electrode and said second gate electrode; introducing said N impurity type at a third concentration into said P type well region, said P impurity type at said third concentration defining first source/drain regions; and forming second sidewall spacers on said first sidewall spacers; introducing said N impurity type at a fourth concentration into said P type well region to further define said first source/drain regions; introducing said P impurity type at a fifth concentration into said N type well region to define second source/drain regions; and wherein said first LDD region extends under a first portion L SA1 of said first sidewall spacers on said edges of said first gate electrode and extends under a portion L G1 of said first gate electrode, and said first source/drain region extends under a second portion of said first sidewall spacers on said edges of said first gate electrode, said portion L G1 being of greater length than said first portion L SA1 , and wherein said portion L G1 is greater than a width of said second sidewall spacers.

Claim 2

A method of forming a complementary metal oxide semiconductor (CMOS) integrated circuit device, said method comprising: providing a semiconductor substrate comprising a P type well region and a N type well region, a first gate dielectric layer overlying said P type well region and a second gate dielectric layer overlying said N type well region, a first gate electrode overlying said first gate dielectric layer and a second gate electrode overlying said second gate dielectric layer; introducing a N impurity type at a first concentration into said P type well region and introducing a P impurity type at a second concentration into said N type well region, said N impurity type in said P type well region defining a first LDD region and said P impurity type in said N type well region defining a second LDD region; forming first sidewall spacers on edges of said first gate electrode and said second gate electrode; introducing said N impurity type at a third concentration into said P type well region, said P impurity type at said third concentration defining first source/drain regions; and forming second sidewall spacers on said first sidewall spacers; introducing said N impurity type at a fourth concentration into said P type well region to further define said first source/drain regions; introducing said P impurity type at a fifth concentration into said N type well region to define second source/drain regions; and wherein said first LDD region extends under a first portion L SA1 of said first sidewall spacers on said edges of said first gate electrode and extends under a portion L G1 of said first gate electrode, and said first source/drain region extends under a second portion of said first sidewall spacers on said edges of said first gate electrode, said portion L G1 being of greater length than said first portion L SA1 , and wherein said portion L G1 is greater than a width of said second sidewall spacers.

Claim 16

A method of forming a complementary metal oxide semiconductor (CMOS) integrated circuit device, said method comprising: providing a semiconductor substrate comprising a first well region and a second well region, a first gate dielectric layer overlying said first well region and a second gate dielectric layer overlying said second well region, a first gate electrode overlying said first gate dielectric layer and a second gate electrode overlying said second gate dielectric layer; introducing a first impurity type at a first concentration into said first well region, said first impurity type in said first well region defining a first LDD region; forming first sidewall spacers on edges of said first gate electrode and said second gate electrode; introducing said first impurity type at a second concentration into said first well region, said first impurity type at said second concentration defining first source/drain regions; introducing said first impurity type at a third concentration into said first well region to form second source/drain regions; introducing at an angle of less than about 60 degrees a second impurity type at a fourth concentration into said second well region, said second impurity type in said second well region defining a second LDD region; and forming second sidewall spacers on said first sidewall spacers; and wherein said first LDD region extends under a first portion L SA1 of said first sidewall spacers on said edges of said first gate electrode and extends under a portion L G1 of said first gate electrode, said second sidewall spacers having a width less than said portion L G1 .

Claim 17

A method of forming a complementary metal oxide semiconductor (CMOS) integrated circuit device, said method comprising: providing a semiconductor substrate comprising a first well region and a second well region, a first gate dielectric layer overlying said first well region and a second gate dielectric layer overlying said second well region, a first gate electrode overlying said first gate dielectric layer and a second gate electrode overlying said second gate dielectric layer; introducing a first impurity type at a first concentration into said first well region, said first impurity type in said first well region defining a first LDD region; forming first sidewall spacers on edges of said first gate electrode and said second gate electrode; introducing said first impurity type at a second concentration into said first well region, said first impurity type at said second concentration defining first source/drain regions; introducing said first impurity type at a third concentration into said first well region to form second source/drain regions; introducing at an angle of less than about 60 degrees a second impurity type at a fourth concentration into said second well region, said second impurity type in said second well region defining a second LDD region; and forming second sidewall spacers on said first sidewall spacers; and wherein said first LDD region extends under a first portion L SA1 of said first sidewall spacers on said edges of said first gate electrode and extends under a portion L G1 of said first gate electrode, said second sidewall spacers having a width less than said portion L G1 .