US5949112A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuits with tub-ties
Assignee: Nokia of America Corp
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Filing: 1998-05-28
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Granted: 1999-09-07
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Expires: 2018-05-28
Abstract
Abstract An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type. In accordance with another aspect of our invention, a reduced-mask-count CMOS IC process includes forming the isolating regions so that each has a protrusion which extends over the surface regions where the peripheral sections of the cap portion are to be formed. Then, a combination of ion implantation energies and concentrations, as well as suitable PR masking, in conjunction with the shape of the isolating regions, enables selective doping of the pedestal portion.
Inventors
- 👤 Hans-Joachim Ludwig Gossmann
- 👤 Thi-Hong-Ha Vuong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:53
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; H10P; H10P30/00; H10P30/20; H10P30/22; H10W10/0125; H10W10/0126; H10W10/0127; H10W10/031; H10W10/10; H10W10/13; H10W10/30
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
88 words
An integrated circuit comprising: a tub of a first conductivity type disposed in a semiconductor body, at least one transistor embedded in said tub, a pair of isolating regions, and a tub-tie region disposed between said isolating regions, said tub-tie region comprising a cap portion of said first conductivity type and an underlying buried pedestal portion of a second conductivity type, said cap portion surrounding at least a top section of said pedestal portion so that a conducting path is formed between said cap portion and said tub.
Claim 2
Dependent Claim
88 words
An integrated circuit comprising: a tub of a first conductivity type disposed in a semiconductor body, at least one transistor embedded in said tub, a pair of isolating regions, and a tub-tie region disposed between said isolating regions, said tub-tie region comprising a cap portion of said first conductivity type and an underlying buried pedestal portion of a second conductivity type, said cap portion surrounding at least a top section of said pedestal portion so that a conducting path is formed between said cap portion and said tub.
Claim 3
Dependent Claim
49 words
The invention of claim 1 wherein said cap portion is wider than said top section of said pedestal portion, and wherein said cap portion comprises a central section which is more heavily doped than said pedestal portion and peripheral sections which are less heavily doped than said central section.
Claim 4
Dependent Claim
38 words
The invention of claim 2 wherein said isolating regions each has a protrusion, said protrusions extending toward one another over said peripheral sections, said peripheral sections separating said central section and said pedestal portion from said isolating regions.
Claim 5
Dependent Claim
186 words
A CMOS integrated circuit comprising: a p-type tub and an n-type tub disposed in a semiconductor body, at least one NMOS transistor embedded in said p-type tub, a first pair of isolating regions, a first tub-tie region disposed between said first isolating regions and coupled to said p-type tub, said first tub-tie region comprising a first p-type cap portion and an underlying buried n-type first pedestal portion, at least a top section of said first pedestal portion being surrounded by said first cap portion so that a first conducting path is formed between said first cap portion and said p-type tub; and at least one PMOS transistor embedded in said n-type tub, a second pair of isolating regions, a second tub-tie region disposed between said second isolating regions and coupled to said n-type tub, said second tub-tie region comprising a second n-type cap portion and an underlying buried p-type second pedestal portion, at least a top section of said second pedestal portion being surrounded by said second cap portion so that a second conducting path is formed between said second cap portion and said n-type tub.
Claim 6
Dependent Claim
186 words
A CMOS integrated circuit comprising: a p-type tub and an n-type tub disposed in a semiconductor body, at least one NMOS transistor embedded in said p-type tub, a first pair of isolating regions, a first tub-tie region disposed between said first isolating regions and coupled to said p-type tub, said first tub-tie region comprising a first p-type cap portion and an underlying buried n-type first pedestal portion, at least a top section of said first pedestal portion being surrounded by said first cap portion so that a first conducting path is formed between said first cap portion and said p-type tub; and at least one PMOS transistor embedded in said n-type tub, a second pair of isolating regions, a second tub-tie region disposed between said second isolating regions and coupled to said n-type tub, said second tub-tie region comprising a second n-type cap portion and an underlying buried p-type second pedestal portion, at least a top section of said second pedestal portion being surrounded by said second cap portion so that a second conducting path is formed between said second cap portion and said n-type tub.
Claim 7
Dependent Claim
55 words
The invention of claim 4 wherein each of said cap portions is wider than the top section of its corresponding pedestal portion, and wherein each of said cap portions has a central section which is more heavily doped than said corresponding pedestal portion and peripheral sections which are less heavily doped than said central section.
Claim 8
Dependent Claim
23 words
The invention of claim 4 wherein said first and second pairs of isolating regions have an isolating region in common with one another.
Claim 9
Dependent Claim
38 words
The invention of claim 4 wherein said isolating regions each has a protrusion, said protrusions extending toward one another over said peripheral sections, said peripheral sections separating said central section and said pedestal portion from said isolating regions.
Claim 10
Dependent Claim
16 words
The invention of claim 1 wherein said cap portion physically contacts each of said isolating regions.
Claim 11
Dependent Claim
31 words
The invention of claim 4 wherein said first cap portion physically contacts each of said first isolating regions, and said second cap portion physically contacts each of said second isolating regions.
References Cited (Backward Citations)
US4905073A
Cited
US5571745A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-06 | 2003-03-08 | 2003-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-06 | 2007-03-08 | 2007-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-06 | 2011-03-08 | 2011-09-07 | $7700.00 | Window Closed / Lapsed |