US6020231A
Expired / Lapsed
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Method for forming LDD CMOS
Assignee: Promos Technologies Inc
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Filing: 1997-03-18
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Granted: 2000-02-01
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Expires: 2017-03-18
Abstract
Abstract A method for fabricating a CMOS integrated circuit device with less masking steps than a conventional device. The present method includes a step of providing a semiconductor substrate with a well region, a gate dielectric layer, and a polysilicon gate electrode. The gate dielectric layer is overlying the well region, and the polysilicon gate electrode is overlying the gate dielectric layer. The present method also includes forming a first thermal oxide thickness overlying the polysilicon gate electrode layer and a second thermal oxide thickness overlying exposed regions. The first thermal oxide thickness is greater than the second thermal oxide thickness, and both layers are defined during the same step. A mask exposes first LDD regions and first source drain regions. The present method then angle implants a first impurity through the first thermal oxide thickness and the second thermal oxide thickness, and implants a second impurity through the second thermal oxide thickness, thereby forming the completed source/drain region in a single masking step.
Inventors
- 👤 Chih-Hsien Wang
- 👤 Min-Liang Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:00
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
221 words
A method of forming a lightly doped drain region (LDD) in an integrated circuit device comprising: providing a semiconductor substrate comprising a first well region, a first gate dielectric layer, and a first polysilicon gate electrode, said first gate dielectric layer overlying said first well region, and said first polysilicon gate electrode overlying said first gate dielectric layer; said first polysilicon gate electrode having a length of about 0.35 micron and less; forming a first thermal oxide thickness overlying said first polysilicon gate electrode layer and a second thermal oxide thickness overlying exposed regions of said first gate dielectric layer, said first thermal oxide thickness being greater than said second thermal oxide thickness; angle implanting a first impurity through said first thermal oxide thickness and said second thermal oxide thickness into said first well region to form first LDD regions; and implanting a second impurity through said second thermal oxide thickness into said first well region to form first source/drain regions; wherein said first gate electrode includes an edge overlying said first gate dielectric layer, said edge having a substantially round corner region which reduces gate edge stress on said first gate dielectric layer, said substantially round corner including a radius of curvature of about 250 Å and greater to reduce a gate edge stress, thereby improving said gate dielectric layer.
Claim 2
Independent Claim
221 words
A method of forming a lightly doped drain region (LDD) in an integrated circuit device comprising: providing a semiconductor substrate comprising a first well region, a first gate dielectric layer, and a first polysilicon gate electrode, said first gate dielectric layer overlying said first well region, and said first polysilicon gate electrode overlying said first gate dielectric layer; said first polysilicon gate electrode having a length of about 0.35 micron and less; forming a first thermal oxide thickness overlying said first polysilicon gate electrode layer and a second thermal oxide thickness overlying exposed regions of said first gate dielectric layer, said first thermal oxide thickness being greater than said second thermal oxide thickness; angle implanting a first impurity through said first thermal oxide thickness and said second thermal oxide thickness into said first well region to form first LDD regions; and implanting a second impurity through said second thermal oxide thickness into said first well region to form first source/drain regions; wherein said first gate electrode includes an edge overlying said first gate dielectric layer, said edge having a substantially round corner region which reduces gate edge stress on said first gate dielectric layer, said substantially round corner including a radius of curvature of about 250 Å and greater to reduce a gate edge stress, thereby improving said gate dielectric layer.
Claim 3
Dependent Claim
17 words
The method of claim 1 wherein said first impurity and said second impurity comprise P type materials.
Claim 4
Dependent Claim
17 words
The method of claim 1 wherein said first impurity and said second impurity comprise N type materials.
Claim 5
Dependent Claim
31 words
The method of claim 1 wherein said angle implanting step occurs at an angle ranging from about 20 degrees to about 60 degrees from a line perpendicular to a channel region.
Claim 6
Dependent Claim
30 words
The method of claim 1 wherein said implanting step occurs at an angle ranging from about 0 degrees to about 7 degrees from a line perpendicular to a channel region.
Claim 7
Dependent Claim
20 words
The method of claim 1 wherein said first thermal oxide thickness ranges from about 200 Å to about 400 Å.
Claim 8
Dependent Claim
20 words
The method of claim 1 wherein said second thermal oxide thickness ranges from about 100 Å to about 300 Å.
Claim 9
Dependent Claim
223 words
The method of claim 1 wherein said semiconductor substrate further comprises a second well region, a second gate dielectric layer, and a second polysilicon gate electrode, said second dielectric layer overlying said second well region, and said second polysilicon gate electrode overlying said second gate dielectric layer, said second polysilicon gate electrode having length about 0.35 micron and less, said method further comprising steps: forming a third thermal oxide thickness overlying said second polysilicon gate electrode and a fourth thermal oxide thickness overlying exposed regions of said second gate dielectric layer, said third thermal oxide thickness being greater than said fourth thermal oxide thickness; angle implanting a third impurity through said third thermal oxide thickness and said fourth thermal oxide thickness into said second well region to form second LDD regions; and implanting a third impurity through said third thermal oxide thickness into said second well region to form second source/drain regions; wherein said second gate electrode includes an edge overlying said second rate dielectric layer, said edge having a substantially round corner region which reduces gate edge stress on said second gate dielectric layer, said substantially round corner of said second gate electrode including a radius of curvature of about 250 Å and greater to reduce a gate edge stress of said second gate electrode, thereby improving said second gate dielectric layer.
Claim 10
Dependent Claim
31 words
The method of claim 8 wherein said angle implanting step occurs at an angle ranging from about 20 degrees to about 60 degrees from a line perpendicular to a channel region.
Claim 11
Dependent Claim
30 words
The method of claim 8 wherein said implanting step occurs at an angle ranging from about 0 degrees to about 7 degrees from a line perpendicular to a channel region.
Claim 12
Dependent Claim
20 words
The method of claim 8 wherein said third thermal oxide thickness ranges from about 200 Å to about 400 Å.
Claim 13
Dependent Claim
20 words
The method of claim 8 wherein said second thermal oxide thickness ranges from about 100 Å to about 300 Å.
References Cited (Backward Citations)
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