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US6649460B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Fabricating a substantially self-aligned MOSFET

Assignee: Google LLC
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Filing: 2001-10-25
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Granted: 2003-11-18
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Expires: 2021-10-25
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Abstract

Abstract The present invention includes methods and structures for forming at least a substantially self-aligned MOSFET. According to the present invention, a method of fabricating a semiconductor device includes providing a substrate; providing first materials (such as a first polysilicon) having horizontal surfaces and also having opposed vertical surfaces forming a trench; providing a second material (such as a second polysilicon) in the trench and over the vertical and horizontal surfaces, the second material having a substantially (eg, ±10%) uniform thickness so as to form a notch over the trench; providing a masking material (such as an oxide or a nitride) into the notch, and then removing the second material using the masking material as a mask in a direction toward the first material, so that a vertical surface of one of the first materials is at least substantially aligned with a vertical surface of the second material.

Inventors

  • 👤 Effendi Leobandung

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 19:33
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; H10D30/601; H10D30/6704; H10D30/6708; H10D30/6713; H10D30/6715; H10D30/6729; H10D30/673; H10D30/6737; H10D30/674; H10D30/6741; H10D30/6743; H10D62/00; H10D62/01; H10D62/021; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D64/017; H10D64/021; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D30/01; H10D30/021; H10D30/0212; H10P; H10P30/00; H10P30/20; H10P30/222

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 118 words
A method of fabricating a semiconductor transistor device, comprising: providing a substrate; providing first materials having horizontal surfaces and also having opposed vertical surfaces forming a trench; providing a second material in the trench and over the vertical and horizontal surfaces, the second material having a substantially uniform thickness so as to form a notch over the trench; providing a masking material into the notch and planarizing, where the masking material is an insulator, and then removing the second material using the masking material as a mask in a direction toward the first material, so that a vertical surface of one of the first materials is at least substantially aligned with a vertical surface of the second material.
Claim 2
Independent Claim 118 words
A method of fabricating a semiconductor transistor device, comprising: providing a substrate; providing first materials having horizontal surfaces and also having opposed vertical surfaces forming a trench; providing a second material in the trench and over the vertical and horizontal surfaces, the second material having a substantially uniform thickness so as to form a notch over the trench; providing a masking material into the notch and planarizing, where the masking material is an insulator, and then removing the second material using the masking material as a mask in a direction toward the first material, so that a vertical surface of one of the first materials is at least substantially aligned with a vertical surface of the second material.
Claim 3
Dependent Claim 32 words
The method as claimed in claim 1 , further comprising providing layers on the on the opposed vertical surfaces of the first materials prior to said step of providing a second material.
Claim 4
Dependent Claim 19 words
The method as claimed in claim 1 , wherein said step of providing first materials comprises providing polysilicon layers.
Claim 5
Dependent Claim 21 words
The method as claimed in claim 1 , wherein said step of providing a second material comprises providing a polysilicon layer.
Claim 6
Dependent Claim 25 words
The method as claimed in claim 1 , wherein said step of providing a masking material comprises providing a layer of oxide into the notch.
Claim 7
Dependent Claim 25 words
The method as claimed in claim 1 , wherein said step of providing a masking material comprises providing a layer of nitride into the notch.
Claim 8
Dependent Claim 27 words
The method as claimed in claim 1 , wherein said step of removing the second material comprises wet etching a polysilicon layer having the substantially uniform thickness.
Claim 9
Dependent Claim 44 words
The method as claimed in claim 1 , wherein each of the first materials comprises a first polysilicon material, and the second material comprises a second polysilicon material, and wherein said method further comprises providing phosphorus materials in the first and second polysilicon materials.
Claim 10
Dependent Claim 20 words
The method as claimed in claim 1 , wherein said step of providing a substrate comprises providing a silicon substrate.
Claim 11
Dependent Claim 20 words
The method as claimed in claim 1 , wherein said step of providing a substrate comprises providing a silicon-on-insulator substrate.
Claim 12
Dependent Claim 50 words
The method as claimed in claim 1 , wherein said step of removing comprises etching the second material on two sides of the masking material in a direction toward the first materials, so that vertical surfaces of the first materials are substantially aligned with vertical surfaces of the second material.
Claim 13
Independent Claim 223 words
A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate; disposing a first oxide layer on the substrate; disposing a nitride layer on the first oxide layer; removing portions of the first layers; removing portions of the substrate adjacent to the remaining first layers; disposing side walls on substantially coplanar surfaces of the first layers and the substrate; disposing second oxide layers on surfaces of the substrate which are substantially normal to the side walls; removing the side walls; disposing and planarizing a first layer of polysilicon on the second oxide layers; disposing a third oxide layer on the layer of polysilicon and on the nitride layer; removing the third oxide layer from a top of the nitride layer; removing the nitride layer to form a trench; disposing a second layer of polysilicon having a substantially uniform thickness over the trench and over the third oxide layer, so that the second layer of polysilicon forms a notch; disposing and planarizing a masking material into the notch so that the masking material substantially fills the notch; and then removing the second layer of polysilicon immediately adjacent to the masking material in a direction normal to the first layer of polysilicon, so that a vertical surface of the second polysilicon layer is substantially coplanar with a vertical surface of the first polysilicon layer.
Claim 14
Independent Claim 223 words
A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate; disposing a first oxide layer on the substrate; disposing a nitride layer on the first oxide layer; removing portions of the first layers; removing portions of the substrate adjacent to the remaining first layers; disposing side walls on substantially coplanar surfaces of the first layers and the substrate; disposing second oxide layers on surfaces of the substrate which are substantially normal to the side walls; removing the side walls; disposing and planarizing a first layer of polysilicon on the second oxide layers; disposing a third oxide layer on the layer of polysilicon and on the nitride layer; removing the third oxide layer from a top of the nitride layer; removing the nitride layer to form a trench; disposing a second layer of polysilicon having a substantially uniform thickness over the trench and over the third oxide layer, so that the second layer of polysilicon forms a notch; disposing and planarizing a masking material into the notch so that the masking material substantially fills the notch; and then removing the second layer of polysilicon immediately adjacent to the masking material in a direction normal to the first layer of polysilicon, so that a vertical surface of the second polysilicon layer is substantially coplanar with a vertical surface of the first polysilicon layer.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2006-11-17 2007-05-19 2007-11-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2010-11-17 2011-05-19 2011-11-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2014-11-17 2015-05-19 2015-11-18 $7700.00 Window Closed / Lapsed

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