US5504033A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming recessed oxide isolation containing deep and shallow trenches
Assignee: Intersil Corp
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Filing: 1994-11-15
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Granted: 1996-04-02
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Expires: 2014-11-15
Abstract
Abstract Recessed isolation oxide is deposited in shallow trenches simultaneoulsy with oxide deposition in deep isolation trenches. A single planarization of both trench fillings provides efficient recessed isolation oxide without bird's beak or bird's head problems of LOCOS isolation oxide. Self-aligned trench filling by successive conformal depositions of oxide and polysilicon followed by planarization to remove polysilicon away from the trenches. The the remaining polysilicon may be used as an oxide etch mask to remove all of the oxide except in the trenches.
Inventors
- 👤 George Bajor
- 👤 Anthony L. Rivoli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:25
CPC Classifications
H; H10; H10P; H10P50/00; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/041; H10W10/061; H10W10/10; H10W10/17; H10W10/181; H10W10/40; H10P90/1914
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
138 words
A method of bonded wafer processing, comprising the steps of: (a) providing a bonded wafer including a device layer, an insulating layer, and a handle wafer; (b) forming trenches of a first depth in said device layer; (c) forming trenches of a second depth in said device layer with said second depth differing from said first depth; (d) forming dielectric simultaneously in said trenches of a first depth and in said trenches of a second depth, said dielectric layer of thickness greater than said second depth, less than said first depth and less than half of the width of said trenches of a first depth; and (e) after said forming dielectric, planarizing said dielectric to remove said dielectric on said device layer and outside of both said trenches of a first depth and said trenches of second depth.
Claim 2
Independent Claim
138 words
A method of bonded wafer processing, comprising the steps of: (a) providing a bonded wafer including a device layer, an insulating layer, and a handle wafer; (b) forming trenches of a first depth in said device layer; (c) forming trenches of a second depth in said device layer with said second depth differing from said first depth; (d) forming dielectric simultaneously in said trenches of a first depth and in said trenches of a second depth, said dielectric layer of thickness greater than said second depth, less than said first depth and less than half of the width of said trenches of a first depth; and (e) after said forming dielectric, planarizing said dielectric to remove said dielectric on said device layer and outside of both said trenches of a first depth and said trenches of second depth.
Claim 3
Dependent Claim
31 words
The method of claim 1, comprising the further step of: (a) after said forming dielectric but prior to said planarizing, filling said trenches of a first depth only with a semiconductor.
Claim 4
Dependent Claim
41 words
The method of claim 1, wherein: (a) said device layer is silicon; (b) said insulation layer is silicon oxide; (c) said semiconductor is polysilicon; and (d) said trenches of a first depth extend through said device layer to said insulation layer.
Claim 5
Dependent Claim
19 words
The method of claim 3, wherein: (a) said forming dielectric includes a thermal oxidation followed by an oxide deposition.
Claim 6
Dependent Claim
35 words
The method of claim 1, wherein: (a) said device layer is silicon, said insulation layer is silicon oxide; and (b) said trenches of a first depth extend through said device layer to said insulation layer.
Claim 7
Dependent Claim
19 words
The method of claim 5, wherein: (a) said forming dielectric includes a thermal oxidation followed by an oxide deposition.
Claim 8
Independent Claim
217 words
A method of bonded wafer processing, comprising the steps of: (a) providing a bonded wafer including a device layer, an insulation layer, and a handle wafer; (b) forming a barrier layer on said device layer, said barrier layer including a semiconductor sublayer and a dielectric sublayer; (b) forming trenches through said barrier layer and extending a first depth into said device layer; (c) forming trenches through said barrier layer and extending a second depth into said device layer with said second depth differing from said first depth; (d) forming a conformal dielectric layer in said trenches and on said barrier layer, said conformal dielectric layer of thickness greater than said second depth, less than said first depth and less than half of the width of said trenches of a first depth; (e) forming a conformal semiconductor layer on said dielectric layer and filling said trenches of a first depth; (f) polishing said conformal semiconductor layer with said conformal dielectric layer as the polish stop to leave semiconductor portions in said trenches; (g) removing the exposed portion of said dielectric with said semiconductor sublayer as removal stop; (h) removing said semiconductor portions except for said semiconductor filling said trenches of a first depth with said dielectric including said dielectric sublayer as removal stop; and (i) planarizing said dielectric.
Claim 9
Independent Claim
217 words
A method of bonded wafer processing, comprising the steps of: (a) providing a bonded wafer including a device layer, an insulation layer, and a handle wafer; (b) forming a barrier layer on said device layer, said barrier layer including a semiconductor sublayer and a dielectric sublayer; (b) forming trenches through said barrier layer and extending a first depth into said device layer; (c) forming trenches through said barrier layer and extending a second depth into said device layer with said second depth differing from said first depth; (d) forming a conformal dielectric layer in said trenches and on said barrier layer, said conformal dielectric layer of thickness greater than said second depth, less than said first depth and less than half of the width of said trenches of a first depth; (e) forming a conformal semiconductor layer on said dielectric layer and filling said trenches of a first depth; (f) polishing said conformal semiconductor layer with said conformal dielectric layer as the polish stop to leave semiconductor portions in said trenches; (g) removing the exposed portion of said dielectric with said semiconductor sublayer as removal stop; (h) removing said semiconductor portions except for said semiconductor filling said trenches of a first depth with said dielectric including said dielectric sublayer as removal stop; and (i) planarizing said dielectric.
Claim 10
Dependent Claim
22 words
The method of claim 7, wherein: (a) said conformal semiconductor layer is silicon; and (b) said conformal dielectric layer is silicon oxide.
References Cited (Backward Citations)
JPS58169933A
Cited
EP0120614A1
Cited
JPS61228650A
Cited
JPS61256649A
Cited
JPS61289642A
Cited
EP0300569A1
Cited
US5036021A
Cited
JPH01309373A
Cited
JPH0254556A
Cited
US4988639A
Cited
EP0398468A2
Cited
EP0405923A2
Cited
US5173439A
Cited
US5336634A
Cited
US5270265A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-02 | 1999-10-02 | 2000-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-02 | 2003-10-02 | 2004-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-02 | 2007-10-02 | 2008-04-02 | $7700.00 | Window Closed / Lapsed |