Method of making back gate contact for silicon on insulator technology

Claim 1

A method for fabricating silicon devices, in a layer of silicon on a first insulator layer, on a semiconductor substrate, incorporating a back gate contact for said silicon devices, to said semiconductor substrate, comprising the steps of: providing said semiconductor substrate; providing said first insulator layer, on said semiconductor substrate; providing said silicon layer, on said first insulator layer, on said semiconductor substrate; growing a second insulator layer on a surface of said silicon, on said first insulator layer; depositing a first polysilicon layer on said second insulator layer; ion implanting a first conductivity imparting dopant into said first polysilicon layer; patterning of said first polysilicon layer to form polysilicon structures; growing a first sidewall oxide on exposed surfaces of said polysilicon structures; depositing a third insulator layer on said polysilicon structures, and between said polysilicon structures; first photoresist masking to expose a region of said first sidewall oxide, and underlying said polysilicon structures; anisotropic etching of said third insulator layer, of said first sidewall oxide, of said polysilicon structures, of said second insulator layer, and of said silicon layer, in said exposed region of said first photoresist masking, to create a trench; removal of said first photoresist masking; growing a second sidewall oxide on exposed surfaces of said polysilicon structures, and exposed surfaces of said silicon layer, in said trench; depositing a fourth insulator layer at the bottom and sides of said trench, and one a surface of said third insulator layer; anisotropic etching of said fourth insulator layer to form first insulator sidewall spaces on sides of said trench, while removing said fourth insulator layer from the surface of said third insulator layer; anisotropic etching of said first insulator layer, at a bottom of said trench, to extend said trench to a surface of said semiconductor substrate, while thinning said third insulator layer; depositing a second polysilicon layer in said trench, and on the surface of said third insulator layer; removal of said second polysilicon layer from the surface of said third insulator layer; removal of said third insulator layer, and of said first sidewall oxide, from the surface of said polysilicon structures; depositing a third layer of polysilicon on the surface of said third insulator layer, between said polysilicon structures, on the surface of said polysilicon structures, and on a surface of said second polysilicon layer, in said trench; ion implanting a second conductivity imparting dopant into said third polysilicon layer; patterning: of said third polysilicon layer, overlying said second polysilicon layer, in said trench, to form said back gate contact structure; of said third polysilicon layer, overlying said third insulator layer, to form a polysilicon resistor structure; and of said third polysilicon layer and said first polysilicon layer, overlying said second insulator layer, to form polysilicon gates; depositing a fifth insulator layer; anisotropic etching of said fifth insulator layer to form second insulator sidewall spacers on sides of said polysilicon gates, on sides of said polysilicon resistor structure, and on sides of said back gate contact structure; a second photoresist masking to expose only a region of said silicon layer, and said polysilicon gates; ion implanting a third conductivity imparting dopant into said region of said silicon layer, not covered by said polysilicon gates, and not covered by said second photoresist masking; removal of said second photoresist masking; deposition of a sixth insulator layer; opening contact holes in said sixth insulator layer, to said back gate contact structure, to said polysilicon resistor structure, and to said region of said silicon layer; deposition of a metal; and forming metal contact structures to said back gate contact structure, to said polysilicon resistor structure, and to said region of said silicon layer.

Claim 2

A method for fabricating silicon devices, in a layer of silicon on a first insulator layer, on a semiconductor substrate, incorporating a back gate contact for said silicon devices, to said semiconductor substrate, comprising the steps of: providing said semiconductor substrate; providing said first insulator layer, on said semiconductor substrate; providing said silicon layer, on said first insulator layer, on said semiconductor substrate; growing a second insulator layer on a surface of said silicon, on said first insulator layer; depositing a first polysilicon layer on said second insulator layer; ion implanting a first conductivity imparting dopant into said first polysilicon layer; patterning of said first polysilicon layer to form polysilicon structures; growing a first sidewall oxide on exposed surfaces of said polysilicon structures; depositing a third insulator layer on said polysilicon structures, and between said polysilicon structures; first photoresist masking to expose a region of said first sidewall oxide, and underlying said polysilicon structures; anisotropic etching of said third insulator layer, of said first sidewall oxide, of said polysilicon structures, of said second insulator layer, and of said silicon layer, in said exposed region of said first photoresist masking, to create a trench; removal of said first photoresist masking; growing a second sidewall oxide on exposed surfaces of said polysilicon structures, and exposed surfaces of said silicon layer, in said trench; depositing a fourth insulator layer at the bottom and sides of said trench, and one a surface of said third insulator layer; anisotropic etching of said fourth insulator layer to form first insulator sidewall spaces on sides of said trench, while removing said fourth insulator layer from the surface of said third insulator layer; anisotropic etching of said first insulator layer, at a bottom of said trench, to extend said trench to a surface of said semiconductor substrate, while thinning said third insulator layer; depositing a second polysilicon layer in said trench, and on the surface of said third insulator layer; removal of said second polysilicon layer from the surface of said third insulator layer; removal of said third insulator layer, and of said first sidewall oxide, from the surface of said polysilicon structures; depositing a third layer of polysilicon on the surface of said third insulator layer, between said polysilicon structures, on the surface of said polysilicon structures, and on a surface of said second polysilicon layer, in said trench; ion implanting a second conductivity imparting dopant into said third polysilicon layer; patterning: of said third polysilicon layer, overlying said second polysilicon layer, in said trench, to form said back gate contact structure; of said third polysilicon layer, overlying said third insulator layer, to form a polysilicon resistor structure; and of said third polysilicon layer and said first polysilicon layer, overlying said second insulator layer, to form polysilicon gates; depositing a fifth insulator layer; anisotropic etching of said fifth insulator layer to form second insulator sidewall spacers on sides of said polysilicon gates, on sides of said polysilicon resistor structure, and on sides of said back gate contact structure; a second photoresist masking to expose only a region of said silicon layer, and said polysilicon gates; ion implanting a third conductivity imparting dopant into said region of said silicon layer, not covered by said polysilicon gates, and not covered by said second photoresist masking; removal of said second photoresist masking; deposition of a sixth insulator layer; opening contact holes in said sixth insulator layer, to said back gate contact structure, to said polysilicon resistor structure, and to said region of said silicon layer; deposition of a metal; and forming metal contact structures to said back gate contact structure, to said polysilicon resistor structure, and to said region of said silicon layer.

Claim 16

A method for fabricating MOSFET devices, and polysilicon resistors, in a layer of silicon on a first insulator layer, on a semiconductor substrate, incorporating a back gate contact, for said MOSFET device, to said semiconductor substrate, comprising the steps of: providing said semiconductor substrate; providing said first insulator layer, on said semiconductor substrate; growing a second insulator layer, on a surface of said silicon layer, to be used as a gate oxide of said MOSFET device; depositing a first polysilicon layer on said gate oxide; ion implanting a first conductivity imparting dopant into said first polysilicon layer; patterning of said first polysilicon layer to form polysilicon structures; growing a first sidewall oxide on exposed surfaces of said polysilicon structures; depositing a third insulator layer on said polysilicon structures, and between said polysilicon structures; first photoresist masking to expose a region of said first sidewall oxide, and underlying said polysilicon structures; anisotropic etching of said third insulator layer, of said first sidewall oxide, of said polysilicon structures, of said gate oxide, and of said silicon layer, in an exposed region of said first photoresist masking, to create a trench; removal of said first photoresist masking; growing a second sidewall oxide on exposed surfaces of said polysilicon structures, and exposed surfaces of said silicon layer, in said trench; deposition of a fourth insulator layer, on bottom and sides of said trench, and on a surface of said third insulator layer; anisotropic etching of said fourth insulator layer to form trench sidewall spacers, on sides of said trench, and completely removing said fourth insulator layer from the surface of said third insulator layer; anisotropic etching of said first insulator layer, at bottom of said trench, to extend said trench to a surface of said semiconductor substrate, while thinning said third insulator layer; deposition of a second polysilicon layer in said trench, and on the surface of said third insulator layer; removal of said second polysilicon layer from the surface of said third insulator layer, leaving a polysilicon filled trench; removal of said third insulator layer, and said first sidewall oxide, from the surface of said polysilicon structures; deposition of a third layer of polysilicon on the surface of said polysilicon structures, on the third insulator layer, between said polysilicon structures, and on a surface of said polysilicon filled trench; ion implanting a second conductivity imparting dopant into said third polysilicon layer; patterning: of said third polysilicon layer, overlying said polysilicon filled trench, to form said back gate contact structures; of said third polysilicon layer, overlying said third insulator layer, to form a polysilicon resistor structures; and of said third polysilicon layer and said first polysilicon layer, overlying said gate oxide, to form polysilicon gates for said MOSFET device; deposition of a fifth insulator layer; anisotropic etching of said fifth insulator layer to form MOSFET sidewall spacers, on sides of said polysilicon gates, and insulator sidewall spacers on sides of, said polysilicon resistor structures, and on sides of said back gate contact structures; a second photoresist masking to expose MOSFET regions; ion implanting a third conductivity imparting dopant into said MOSFET regions, to create source and drain regions; removal of said second photoresist masking; deposition of a sixth insulator layer; opening contact holes in said sixth insulator layer, to said back gate contact structures, to said polysilicon resistor structures, and to said regions of said MOSFET device; deposition of a metal; and forming metal contact structures to said back gate contact structures, to said polysilicon resistor structures, and to said regions of said MOSFET device.

Claim 17

A method for fabricating MOSFET devices, and polysilicon resistors, in a layer of silicon on a first insulator layer, on a semiconductor substrate, incorporating a back gate contact, for said MOSFET device, to said semiconductor substrate, comprising the steps of: providing said semiconductor substrate; providing said first insulator layer, on said semiconductor substrate; growing a second insulator layer, on a surface of said silicon layer, to be used as a gate oxide of said MOSFET device; depositing a first polysilicon layer on said gate oxide; ion implanting a first conductivity imparting dopant into said first polysilicon layer; patterning of said first polysilicon layer to form polysilicon structures; growing a first sidewall oxide on exposed surfaces of said polysilicon structures; depositing a third insulator layer on said polysilicon structures, and between said polysilicon structures; first photoresist masking to expose a region of said first sidewall oxide, and underlying said polysilicon structures; anisotropic etching of said third insulator layer, of said first sidewall oxide, of said polysilicon structures, of said gate oxide, and of said silicon layer, in an exposed region of said first photoresist masking, to create a trench; removal of said first photoresist masking; growing a second sidewall oxide on exposed surfaces of said polysilicon structures, and exposed surfaces of said silicon layer, in said trench; deposition of a fourth insulator layer, on bottom and sides of said trench, and on a surface of said third insulator layer; anisotropic etching of said fourth insulator layer to form trench sidewall spacers, on sides of said trench, and completely removing said fourth insulator layer from the surface of said third insulator layer; anisotropic etching of said first insulator layer, at bottom of said trench, to extend said trench to a surface of said semiconductor substrate, while thinning said third insulator layer; deposition of a second polysilicon layer in said trench, and on the surface of said third insulator layer; removal of said second polysilicon layer from the surface of said third insulator layer, leaving a polysilicon filled trench; removal of said third insulator layer, and said first sidewall oxide, from the surface of said polysilicon structures; deposition of a third layer of polysilicon on the surface of said polysilicon structures, on the third insulator layer, between said polysilicon structures, and on a surface of said polysilicon filled trench; ion implanting a second conductivity imparting dopant into said third polysilicon layer; patterning: of said third polysilicon layer, overlying said polysilicon filled trench, to form said back gate contact structures; of said third polysilicon layer, overlying said third insulator layer, to form a polysilicon resistor structures; and of said third polysilicon layer and said first polysilicon layer, overlying said gate oxide, to form polysilicon gates for said MOSFET device; deposition of a fifth insulator layer; anisotropic etching of said fifth insulator layer to form MOSFET sidewall spacers, on sides of said polysilicon gates, and insulator sidewall spacers on sides of, said polysilicon resistor structures, and on sides of said back gate contact structures; a second photoresist masking to expose MOSFET regions; ion implanting a third conductivity imparting dopant into said MOSFET regions, to create source and drain regions; removal of said second photoresist masking; deposition of a sixth insulator layer; opening contact holes in said sixth insulator layer, to said back gate contact structures, to said polysilicon resistor structures, and to said regions of said MOSFET device; deposition of a metal; and forming metal contact structures to said back gate contact structures, to said polysilicon resistor structures, and to said regions of said MOSFET device.