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US5908313A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming a transistor

Assignee: Intel Corp
•
Filing: 1996-12-31
•
Granted: 1999-06-01
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Expires: 2016-12-31
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Abstract

Abstract A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.

Inventors

  • 👤 Robert S. Chau
  • 👤 Chia-Hong Jan
  • 👤 Paul Packan
  • 👤 Mitchell C. Taylor

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 14:44
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0275; H10D62/00; H10D62/01; H10D62/021; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131; H10D64/20; H10D64/23; H10D64/251; H10D64/256; H10D64/258; H10D64/259; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10P; H10P30/00; H10P30/20; H10P30/222; H10P30/202; H10P30/204; H10P30/208; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171

Claims Analysis

Total Claims: 21
Claim 1
Independent Claim 80 words
A method of forming a transistor, said method comprising the steps of: forming a gate dielectric layer on a first surface of a semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a pair of recesses in said semiconductor substrate in alignment with the outside edges of said gate electrode; forming a first semiconductor material in said recesses; and after forming said first semiconductor material, forming a dielectric layer in said recess beneath said first semiconductor material.
Claim 2
Independent Claim 80 words
A method of forming a transistor, said method comprising the steps of: forming a gate dielectric layer on a first surface of a semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a pair of recesses in said semiconductor substrate in alignment with the outside edges of said gate electrode; forming a first semiconductor material in said recesses; and after forming said first semiconductor material, forming a dielectric layer in said recess beneath said first semiconductor material.
Claim 3
Dependent Claim 38 words
The method of forming a transistor of claim 1 further comprising the step of: doping said first semiconductor material with dopants; and diffusing said dopants from said first semiconductor material into said substrate and beneath said gate electrode.
Claim 4
Dependent Claim 27 words
The method of forming a transistor of claim 1 further comprising the step of: forming a pair of halo regions through said recesses into said silicon substrate.
Claim 5
Independent Claim 110 words
A method of forming a transistor, said method comprising the steps of: forming a gate dielectric layer on a first surface of the semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a pair of sidewall spacers along opposite sides of said gate electrode; forming a pair of recesses in said semiconductor substrate in alignment with the outside edges of said pair of sidewall spacers; implanting nitrogen atoms into surface of said pair of recesses; selectively depositing semiconductor material onto said nitrogen implanted surface in said pair of recesses to form a pair of source/drain regions; and annealing said substrate to form a silicon nitride dielectric layer.
Claim 6
Independent Claim 110 words
A method of forming a transistor, said method comprising the steps of: forming a gate dielectric layer on a first surface of the semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a pair of sidewall spacers along opposite sides of said gate electrode; forming a pair of recesses in said semiconductor substrate in alignment with the outside edges of said pair of sidewall spacers; implanting nitrogen atoms into surface of said pair of recesses; selectively depositing semiconductor material onto said nitrogen implanted surface in said pair of recesses to form a pair of source/drain regions; and annealing said substrate to form a silicon nitride dielectric layer.
Claim 7
Dependent Claim 21 words
The method of claim 4 wherein said semiconductor material is deposited above and below said first surface of said semiconductor substrate.
Claim 8
Dependent Claim 25 words
The method of claim 4 further comprising the step of implanting a pair of halo regions through said recesses prior to depositing said semiconductor material.
Claim 9
Dependent Claim 29 words
The method of claim 4 further comprising the step of: doping said semiconductor material; and diffusing said dopants from said semiconductor material into said substrate beneath said gate electrode.
Claim 10
Independent Claim 77 words
A method of forming a transistor comprising the steps of: forming a gate dielectric layer on a first surface of the semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a pair of recesses in said semiconductor substrate on opposite sides of said gate electrode; forming a pair of halo regions through said recesses into said silicon substrate and beneath said gate electrode; and forming a first semiconductor material in said pair of recesses.
Claim 11
Independent Claim 77 words
A method of forming a transistor comprising the steps of: forming a gate dielectric layer on a first surface of the semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a pair of recesses in said semiconductor substrate on opposite sides of said gate electrode; forming a pair of halo regions through said recesses into said silicon substrate and beneath said gate electrode; and forming a first semiconductor material in said pair of recesses.
Claim 12
Dependent Claim 32 words
The method of claim 8 further comprising the step of: doping said semiconductor material with dopants; and diffusing said dopants from said first semiconductor material into said substrate beneath said gate electrode.
Claim 13
Dependent Claim 17 words
The method of claim 8 further comprising the step of: forming a dielectric layer in said recesses.
Claim 14
Dependent Claim 25 words
The method claim 10 wherein said step of forming said dielectric layer in said recesses comprises the step of ion implanting nitrogen into said recesses.
Claim 15
Independent Claim 119 words
A method of forming a transistor, said method comprising the steps of: forming a gate dielectric layer on a first surface of semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a pair of sidewall spacers along opposite sides of said gate electrode; forming a pair of recesses in said semiconductor substrate in alignment with the outside edges of said pair of sidewall spacers; implanting atoms of a first element into said substrate in said pair of recesses; selectively depositing semiconductor material onto said substrate in said pair of recesses above said implanted atoms and not onto said sidewall spacers; and forming a dielectric layer from said atoms of said first element placed into said substrate.
Claim 16
Independent Claim 119 words
A method of forming a transistor, said method comprising the steps of: forming a gate dielectric layer on a first surface of semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a pair of sidewall spacers along opposite sides of said gate electrode; forming a pair of recesses in said semiconductor substrate in alignment with the outside edges of said pair of sidewall spacers; implanting atoms of a first element into said substrate in said pair of recesses; selectively depositing semiconductor material onto said substrate in said pair of recesses above said implanted atoms and not onto said sidewall spacers; and forming a dielectric layer from said atoms of said first element placed into said substrate.
Claim 17
Dependent Claim 11 words
The method of claim 12 wherein said first element is nitrogen.
Claim 18
Dependent Claim 11 words
The method of claim 12 wherein said first element is oxygen.
Claim 19
Independent Claim 96 words
A method of forming a transistor, said method comprising the steps: forming a gate dielectric layer on said first surface of said semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a pair of sidewall spacers along opposite sides of said gate electrode; forming a pair of recesses in said semiconductor substrate in alignment with the outside edges of said pair of sidewall spacers; forming a silicon rich dielectric layer onto a surface of said pair of recesses; and depositing semiconductor material onto said silicon rich dielectric layer in said pair of recesses.
Claim 20
Independent Claim 96 words
A method of forming a transistor, said method comprising the steps: forming a gate dielectric layer on said first surface of said semiconductor substrate; forming a gate electrode on said gate dielectric layer; forming a pair of sidewall spacers along opposite sides of said gate electrode; forming a pair of recesses in said semiconductor substrate in alignment with the outside edges of said pair of sidewall spacers; forming a silicon rich dielectric layer onto a surface of said pair of recesses; and depositing semiconductor material onto said silicon rich dielectric layer in said pair of recesses.
Claim 21
Dependent Claim 16 words
The method of claim 15 wherein said dielectric layer is a silicon rich silicon nitride layer.

References Cited (Backward Citations)

US4523213A Cited
US4700454A Cited
US4683637A Cited
US4963502A Cited
US5218221A Cited
US5620912A Cited
US5710450A Cited
US5712173A Cited
US5674760A Cited

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