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US5674760A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming isolation regions in a MOS transistor device

Assignee: United Microelectronics Corp
•
Filing: 1996-02-26
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Granted: 1997-10-07
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Expires: 2016-02-26
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Abstract

Abstract The present invention is directed to a MOS transistor and its method of fabrication. The transistor includes isolating layers below source/drain regions of the transistor. In this manner, lateral diffusion occurring in the source/drain regions can be retarded. Accordingly, the fabricated. MOS transistor has the advantages of shallow junction depth, low junction capacitance, and better punchthrough resistance. Furthermore, since the bulk of the MOS transistor might be connected to a constant voltage, most likely ground, via a contact region, the floating body effects typically encountered in SOI (silicon-on-insulator) devices can be avoided.

Inventors

  • 👤 Gary Hong

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 12:34
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/208; H10P30/209; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/378; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0151; H10D84/02; H10D84/03; H10D84/038; H10P30/22

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 169 words
A method for fabricating a MOS transistor, comprising: providing a silicon substrate of a first conductivity type; forming field oxides on said substrate to define an active region therebetween; subsequently forming a gate dielectric layer over said substrate; forming a conducting layer over said gate dielectric layer; forming a shielding layer on said conducting layer; patterning said conducting layer to form a gate electrode by utilizing said shielding layer as a masking layer; implanting isolating impurities into said substrate using said shielding layer and reacting said isolating impurities to form two isolating layers within said substrate at opposite sides of said gate electrode; implanting impurities of a second conductivity type, different than said first conductivity type, into said substrate to form a pair of source and drain regions disposed above respective regions of said isolating layers; and implanting impurities of the first conductivity type into said substrate outside said active region to form a contact region said contact region formed after forming said pair of source and drain regions.
Claim 2
Independent Claim 169 words
A method for fabricating a MOS transistor, comprising: providing a silicon substrate of a first conductivity type; forming field oxides on said substrate to define an active region therebetween; subsequently forming a gate dielectric layer over said substrate; forming a conducting layer over said gate dielectric layer; forming a shielding layer on said conducting layer; patterning said conducting layer to form a gate electrode by utilizing said shielding layer as a masking layer; implanting isolating impurities into said substrate using said shielding layer and reacting said isolating impurities to form two isolating layers within said substrate at opposite sides of said gate electrode; implanting impurities of a second conductivity type, different than said first conductivity type, into said substrate to form a pair of source and drain regions disposed above respective regions of said isolating layers; and implanting impurities of the first conductivity type into said substrate outside said active region to form a contact region said contact region formed after forming said pair of source and drain regions.
Claim 3
Dependent Claim 13 words
The method as claimed in claim 1, wherein said isolating impurities are oxygen.
Claim 4
Dependent Claim 13 words
The method as claimed in claim 1, wherein said isolating impurities are nitrogen.
Claim 5
Dependent Claim 18 words
The method as claimed in claim 1, wherein said shielding layer is a photoresist layer patterned by photolithography.
Claim 6
Dependent Claim 21 words
The method as claimed in claim 1, wherein said first conductivity type is P-type, and the second conductivity type is N-type.
Claim 7
Dependent Claim 21 words
The method as claimed in claim 1, wherein said first conductivity type is N-type, and said second conductivity type is P-type.

References Cited (Backward Citations)

JPS5955068A Cited
US4700454A Cited
DE3726842A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-10-06 2001-04-07 2001-10-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-10-06 2005-04-07 2005-10-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-10-06 2009-04-07 2009-10-07 $7700.00 Window Closed / Lapsed

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