Micromachined chip scale package

Claim 2

A multi-semiconductor die assembly, comprising: at least one first chip scale semiconductor die package, comprising: at least one first semiconductor die made of a semiconductor material and including an integrated circuit having external electrical connections on an active side thereof; and discrete preformed blank made of the same semiconductor material as the at least one first semiconductor die is made and having a bondable surface having surface dimensions not in excess of surface dimensions of the active side of the at least one first semiconductor die and including apertures preformed therein through which the external electrical connections of the at least one first semiconductor die are accessible, placed over the active side of the at least one first semiconductor die and secured thereto by the bondable surface with a bonding material to form a laminate comprising the at least one first semiconductor die and the discrete preformed blank bonded together; and at least one second chip scale semiconductor die package comprising at least one second semiconductor die made of a semiconductor material and including an integrated circuit having external electrical connections on an active side thereof, the at least one second chip scale semiconductor die package positioned adjacently opposite the at least one first chip scale semiconductor die package in an active side-to-active side facing relationship and at least one of said external electrical connections of the at least one first semiconductor die in electrical communication with at least one of said external electrical connections of the at least one second semiconductor die.

Claim 3

The multi-semiconductor die assembly of claim 1 , wherein the external electrical connections of at least one of the at least one first semiconductor die and the at least one second semiconductor die comprise bond pads.

Claim 4

The multi-semiconductor die assembly of claim 1 , wherein the external electrical connections of the at least one first semiconductor die comprise bond pads and the external electrical connections of the at least one second semiconductor die comprise bond pads.

Claim 5

The multi-semiconductor die assembly of claim 1 , wherein at least one of the at least one first chip scale semiconductor die package and the at least one second chip scale semiconductor die package comprises a plurality of dies.

Claim 6

The multi-semiconductor die assembly of claim 1 , wherein the same semiconductor material of the at least one first chip scale semiconductor die package comprises silicon.

Claim 7

The multi-semiconductor die assembly of claim 1 , wherein the same semiconductor material of the at least one first chip scale semiconductor die package comprises GaAs.

Claim 8

The multi-semiconductor die assembly of claim 1 , wherein at least one of the at least one first chip scale semiconductor die package and the at least one second chip scale semiconductor die package comprises a passivation layer on at least a portion of the active side thereof.

Claim 9

The multi-semiconductor die assembly of claim 7 , wherein the passivation layer on the at least a portion of the active side comprises at least one of an oxide and a nitride.

Claim 10

The multi-semiconductor die assembly of claim 1 , wherein at least a portion of the exterior of the laminate of the at least one first chip scale semiconductor die package is passivated.

Claim 11

The multi-semiconductor die assembly of claim 1 , wherein the external electrical connections of the at least one first semiconductor die comprise bond pads and the apertures of the discrete preformed blank of the at least one first chip scale semiconductor die package are in alignment with the bond pads of the at least one first semiconductor die.

Claim 12

The multi-semiconductor die assembly of claim 1 , further comprising a passivation layer disposed on the active side of at least one of the at least one first semiconductor die and the at least one second semiconductor die.

Claim 13

The multi-semiconductor die assembly of claim 1 , wherein the at least one of said external electrical connections of the at least one first semiconductor die in electrical communication with the at least one of said external electrical connections of the at least one second semiconductor die comprises at least one of electrically conductive solder, electrically conductive epoxy, and electrically conductive polymer.

Claim 14

The multi-semiconductor die assembly of claim 12 , wherein the at least one of said external electrical connections of the at least one first semiconductor die in electrical communication with the at least one of said external electrical connections of the at least one second semiconductor die comprises at least one of an electrically conductive ball, an electrically conductive bump, an electrically conductive pillar, and an electrolessly-plated conductive bump.

Claim 15

The multi-semiconductor die assembly of claim 1 , wherein the at least one second chip scale semiconductor die package comprises: a discrete preformed blank made of the same semiconductor material as the at least one second semiconductor die is made and having a bondable surface having surface dimensions not in excess of surface dimensions of the active side of the at least one second semiconductor die and including apertures preformed therein through which the external electrical connections of the at least one second semiconductor die are accessible, placed over the active side of the at least one second semiconductor die and secured thereto by the bondable surface with a bonding material to form a laminate comprising the at least one second semiconductor die and the discrete preformed blank bonded together.

Claim 16

The multi-semiconductor die assembly of claim 14 , wherein the external electrical connections of at least one of the at least one first semiconductor die and the at least one second semiconductor die comprise bond pads.

Claim 17

The multi-semiconductor die assembly of claim 14 , wherein the external electrical connections of the at least one first semiconductor die comprise bond pads and the external electrical connections of the at least one second semiconductor die comprise bond pads.

Claim 18

The multi-semiconductor die assembly of claim 14 , wherein at least one of the at least one first semiconductcr die and the at least one second semiconductor die comprises a plurality of dies.

Claim 19

The multi-semiconductor die assembly of claim 14 , wherein the same semiconductor material of the at least one second chip scale semiconductor die package comprise s silicon.

Claim 20

The multi-semiconductor die assembly of claim 14 , wherein the same semiconductor material of the at least one second chip scale semiconductor die package comprises GaAs.

Claim 21

The multi-semiconductor die assembly of claim 14 , wherein at least one of the at least one first chip scale semiconductor die package and the at least one second chip scale semiconductor die package comprises a passivation layer on at least a portion of the active side thereof.

Claim 22

The multi-semiconductor die assembly of claim 20 , wherein the passivation layer on the at least a portion of the active side comprises at least one of an oxide and a nitride.

Claim 23

The multi-semiconductor die assembly of claim 14 , wherein at least a portion of the exterior of the laminate of the at least one second chip scale semiconductor die package is passivated.

Claim 24

The multi-semiconductor die assembly of claim 14 , wherein the external electrical connections of the at least one second semiconductor die comprise bond pads and the apertures of the discrete preformed blank of the at least one second chip scale semiconductor die package are in alignment with the bond pads of the at least one second semiconductor die.

Claim 25

The multi-semiconductor die assembly of claim 14 , wherein at least some of the apertures in the discrete preformed blank of the at least one second chip scale semiconductor die package are positioned at locations remote from the external electrical connections of the at least one second semiconductor die.

Claim 26

The multi-semiconductor die assembly of claim 14 , further comprising a passivation layer disposed on the active side of at least one of the at least one first semiconductor die and the at least one second semiconductor die.

Claim 27

The multi-semiconductor die assembly of claim 14 , wherein the at least one of said external electrical connections of the at least one first semiconductor die in electrical communication with the at least one of said external electrical connections of the at least one second semiconductor die comprises at least one of electrically conductive solder, electrically conductive epoxy, and electrically conductive polymer.

Claim 28

The multi-semiconductor die assembly of claim 26 , wherein the at least one of said external electrical connections of the at least one first semiconductor die in electrical communication with the at least one of said external electrical connections of the at least one second semiconductor die comprises at least one of an electrically conductive ball, an electrically conductive bump, an electrically conductive pillar, and an electrolessly-plated conductive bump.

Claim 29

The multi-semiconductor die assembly of claim 14 , wherein the at least one first chip scale semiconductor die package comprises a plurality of first chip scale semiconductor die packages and the at least one second chip scale semiconductor die package comprises a plurality of second chip scale semiconductor die packages.

Claim 30

The multi-semiconductor die assembly of claim 28 , wherein at least one of the group consisting of the plurality of first chip scale semiconductor die packages and the plurality of second chip scale semiconductor die packages comprise unsevered semiconductor dies of at least a portion of a semiconductor wafer.

Claim 31

The multi-semiconductor die assembly of claim 28 , wherein the plurality of first chip scale semiconductor die packages are unsevered from a first semiconductor wafer.

Claim 32

The multi-semiconductor die assembly of claim 28 , wherein the plurality of second chip scale semiconductor die packages are unsevered from a second semiconductor wafer.

Claim 33

The multi-semiconductor die assembly of claim 31 , wherein at least a portion of the first semiconductor wafer is passivated and at least a portion of the second semiconductor wafer is passivated.

Claim 34

A multi-semiconductor die assembly, comprising: at least one first chip scale semiconductor die package, comprising: at least one first semiconductor die made of a semiconductor material and including an integrated circuit having external electrical connections on an active side thereof; and a discrete preformed blank having a bondable surface having surface dimensions not in excess of surface dimensions of the active side of the at least one first semiconductor die and including apertures preformed therein through which the external electrical connections of the at least one first semiconductor die are accessible, placed over the active side of the at least one first semiconductor die and secured thereto by the bondable surface with a bonding material to form a laminate comprising the at least one first semiconductor die and the discrete preformed blank bonded together, wherein at least some of the apertures are positioned in the discrete preformed blank at locations remote from the external electrical connections of the at least one first semiconductor die; and at least one second chip scale semiconductor die package comprising at least one second semiconductor chip made of a semiconductor material and including an integrated circuit having external electrical connections on an active side thereof, the at least one second chip scale semiconductor die package positioned adjacently opposite the at least one first chip scale semiconductor die package in an active side-to-active side facing relationship and at least one of said external electrical connections of the at least one first semiconductor die in electrical communication with at least one of said external electrical connections of the at least one second semiconductor die.

Claim 35

A multi-semiconductor die assembly, comprising: at least one first chip scale semiconductor die package, comprising: at least one first semiconductor die made of a semiconductor material and including an integrated circuit having external electrical connections on an active side thereof; and a discrete preformed blank having a bondable surface having surface dimensions not in excess of surface dimensions of the active side of the at least one first semiconductor die and including apertures preformed therein through which the external electrical connections of the at least one first semiconductor die are accessible, placed over the active side of the at least one first semiconductor die and secured thereto by the bondable surface with a bonding material to form a laminate comprising the at least one first semiconductor die and the discrete preformed blank bonded together, wherein at least some of the apertures are positioned in the discrete preformed blank at locations remote from the external electrical connections of the at least one first semiconductor die; and at least one second chip scale semiconductor die package comprising at least one second semiconductor chip made of a semiconductor material and including an integrated circuit having external electrical connections on an active side thereof, the at least one second chip scale semiconductor die package positioned adjacently opposite the at least one first chip scale semiconductor die package in an active side-to-active side facing relationship and at least one of said external electrical connections of the at least one first semiconductor die in electrical communication with at least one of said external electrical connections of the at least one second semiconductor die.

Claim 36

The multi-semiconductor die assembly of claim 33 , wherein the external electrical connections of at least one of the at least one first semiconductor die and the at least one second semiconductor die comprise bond pads.

Claim 37

The multi-semiconductor die assembly of claim 33 , wherein at least one of the at least one first chip scale semiconductor die package and the at least one second chip scale semiconductor die package comprises a plurality of dies.

Claim 38

The multi-semiconductor die assembly of claim 33 , wherein the semiconductor material of the at least one first chip scale semiconductor die package comprises at least one of silicon and GaAs.

Claim 39

The multi-semiconductor die assembly of claim 33 , wherein the discrete preformed blank of the at least one first chip scale semiconductor die package comprises at least one of silicon and GaAs.

Claim 40

The multi-semiconductor die assembly of claim 33 , wherein the discrete preformed blank of the at least one first chip scale semiconductor die package is made of the same semiconductor material as the at least one first semiconductor die.

Claim 41

The multi-semiconductor die assembly of claim 38 , wherein the same semiconductor material of the at least one first chip scale semiconductor die package comprises at least one of silicon and GaAs.

Claim 42

The multi-semiconductor die assembly of claim 33 , wherein at least a portion of at least one of the exterior of the laminate of the at least one first chip scale semiconductor die package is passivated.

Claim 43

The multi-semiconductor die assembly of claim 33 , wherein the apertures of the discrete preformed blank of the at least one first chip scale semiconductor die package are in alignment with the external electrical connections of the at least one second semiconductor die.

Claim 44

The multi-semiconductor die assembly of claim 33 , further comprising a passivation layer disposed on at least a portion of the active side of at least one of the at least one first semiconductor die and the at least one second semiconductor die.

Claim 45

The multi-semiconductor die assembly of claim 33 , wherein the at least one of said external electrical connections of the at least one first semiconductor die in electrical communication with the at least one of said external electrical connections of the at least one second semiconductor die comprises at least one of electrically conductive solder, electrically conductive epoxy, and electrically conductive polymer.

Claim 46

The multi-semiconductor die assembly of claim 43 , wherein the at least one of said external electrical connections of the at least one first semiconductor die in electrical communication with the at least one of said external electrical connections of the at least one second semiconductor die comprises at least one of an electrically conductive ball, an electrically conductive bump, an electrically conductive pillar, and an electrolessly-plated conductive bump.

Claim 47

The multi-semiconductor die assembly of claim 33 , further comprising circuit traces extending from the external electrical connections of the at least one first semiconductor die to the remote aperture locations of the discrete preformed blank of the at least one first chip scale semiconductor die package.

Claim 48

The multi-semiconductor die assembly of claim 45 , wherein the circuit traces are at least partially disposed on the active side of the at least one first semiconductor die.

Claim 49

The multi-semiconductor die assembly of claim 45 , wherein the circuit traces are at least partially disposed on the discrete preformed blank of the at least one first chip scale semiconductor die package.

Claim 50

The multi-semiconductor die assembly of claim 33 , wherein the at least one second chip scale semiconductor die package comprises: a discrete preformed blank made having a bondable surface having surface dimensions not in excess of surface dimensions of the active side of the at least one second semiconductor die and including apertures preformed therein through which the external electrical connections of the at least one second semiconductor die are accessible, placed over the active side of the at least one second semiconductor die and secured thereto by the bondable surface with a bonding material to form a laminate comprising the at least one second semiconductor die and the discrete preformed blank bonded together.

Claim 51

The multi-semiconductor die assembly of claim 48 , wherein the external electrical connections of at least one of the at least one first semiconductor die and the at least one second semiconductor die comprise bond pads.

Claim 52

The multi-semiconductor die assembly of claim 48 , wherein at least one of the at least one first semiconductor die and the at least one second semiconductor die comprises a plurality of dies.

Claim 53

The multi-semiconductor die assembly of claim 48 , wherein the semiconductor material of at least one of the at least one second chip scale semiconductor die package comprises at least one of the group consisting of silicon, GaAs, ceramic material, and mullite.

Claim 54

The multi-semiconductor die assembly of claim 48 , wherein the discrete preformed blank of the at least one second chip scale semiconductor die package comprises at least one of the group consisting of silicon, GaAs, ceramic material, and mullite.

Claim 55

The multi-semiconductor die assembly of claim 48 , wherein the discrete preformed blank of the at least one second chip scale semiconductor die package is made of the same semiconductor material as the at least one second semiconductor die.

Claim 56

The multi-semiconductor die assembly of claim 53 , wherein the same semiconductor material of the at least one second chip scale semiconductor die package comprises at least one of silicon and GaAs.

Claim 57

The multi-semiconductor die assembly of claim 48 , wherein at least a portion of the exterior of the laminate of the at least one second chip scale semiconductor die package is passivated.

Claim 58

The multi-semiconductor die assembly of claim 48 , wherein at least some of the apertures in the discrete preformed blank of the second chip scale semiconductor die package are positioned at locations in alignment with the at least some of the apertures in the discrete preformed blank of the at least one first chip scale semiconductor die package.

Claim 59

The multi-semiconductor die assembly of claim 48 , wherein at least some of the apertures in the discrete preformed blank of the second chip scale semiconductor die package are positioned at locations remote from the external electrical connections of the at least one second semiconductor die.

Claim 60

The multi-semiconductor die assembly of claim 57 , further comprising circuit traces extending from the external electrical connections of the at least one second semiconductor die to the remote aperture locations of the discrete preformed blank of the at least one second chip scale semiconductor die package.

Claim 61

The multi-semiconductor die assembly of claim 58 , wherein the circuit traces are at least partially disposed on the active side of the at least one second semiconductor die.

Claim 62

The multi-semiconductor die assembly of claim 58 , wherein the circuit traces are at least partially disposed on the discrete preformed blank of the at least one second chip scale semiconductor die package.

Claim 63

The multi-semiconductor die assembly of claim 48 , further comprising a passivation layer disposed on the active side of at least one of the at least one first semiconductor die and the at least one second semiconductor die.

Claim 64

The multi-semiconductor die assembly of claim 48 , wherein the at least one of said external electrical connections of the at least one first semiconductor die in electrical communication with the at least one of said external electrical connections of the at least one second semiconductor die comprises at least one of electrically conductive solder, electrically conductive epoxy, and electrically conductive polymer.

Claim 65

The multi-semiconductor die assembly of claim 62 , wherein the at least one of said external electrical connections of the at least one first semiconductor die in electrical communication with the at least one of said external electrical connections of the at least one second semiconductor die comprises at least one of an electrically conductive ball, an electrically conductive bump, an electrically conductive pillar, and an electrolessly-plated conductive bump.

Claim 66

The multi-semiconductor die assembly of claim 48 , wherein the at least one first chip scale semiconductor die package comprises a plurality of first chip scale semiconductor die packages and the at least one second chip scale semiconductor die package comprises a plurality of second chip scale semiconductor die packages.

Claim 67

The multi-semiconductor die assembly of claim 64 , wherein at least one of the group consisting of the plurality of first chip scale semiconductor die packages and the plurality of second chip scale semiconductor die packages comprise unsevered semiconductor dies of at least a portion of a semiconductor wafer.

Claim 68

The multi-semiconductor die assembly of claim 64 , wherein the plurality of first chip scale semiconductor die packages are unsevered from a first semiconductor wafer.

Claim 69

The multi-semiconductor die assembly of claim 64 , wherein the plurality of second chip scale semiconductor die packages are unsevered from a second semiconductor wafer.

Claim 70

The multi-semiconductor die assembly of claim 67 , wherein at least a portion of the first semiconductor wafer is passivated and at least a portion of the second semiconductor wafer is passivated.