US5579573A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating an undercoated chip electrically interconnected to a substrate
Assignee: Visteon Global Technologies Inc
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Filing: 1994-10-11
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Granted: 1996-12-03
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Expires: 2014-10-11
Abstract
Abstract ` Method for fabricating an undercoated chip electrically interconnected to a substrate. The method includes the initial step of depositing a predetermined quantity of a liquid undercoat material onto the chip or the substrate. The method continues with the step of interconnecting the chip to the substrate so as to form an electrical interconnection bond therebetween. Finally, the method concludes with the step of heating, reflowing and curing the undercoat material during or after the step of electrically interconnecting the chip to the substrate.
Inventors
- 👤 Jay D. Baker
- 👤 Cuong V. Pham
- 👤 Robert E. Belke, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:04
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/30; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/15; H10W72/01; H10W72/013; H10W72/01331; H10W72/071; H10W72/073; H10W72/07331; H10W72/07337; H10W72/07338; H10W72/20; H10W72/251; H10W72/253; H10W72/851; H10W72/853; H10W72/856; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144; Y10T29/49146
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
164 words
A method of fabricating an undercoated chip electrically interconnected to a substrate, the chip having a first and second surface and having electrical interconnections on the first surface, and the substrate having a first and second surface and having means for interconnecting on the first surface corresponding to the electrical interconnections, the method comprising: (a) depositing a predetermined quantity of an undercoat material having sufficient low expansion fillers to achieve a linear coefficient of thermal expansion (CTE) matching a CTE of the electrical interconnections onto the first surface of one of the chip and the substrate; (b) etching the undercoat material from the first surface of the one of the chip and the substrate until the electrical interconnections or the means for interconnecting are exposed; (c) connecting the electrical interconnections of the chip to the means for interconnecting of the substrate so as to form an electrical interconnection bond therebetween; and (d) heating, reflowing and curing the undercoat material during or after step (c).
Claim 2
Independent Claim
164 words
A method of fabricating an undercoated chip electrically interconnected to a substrate, the chip having a first and second surface and having electrical interconnections on the first surface, and the substrate having a first and second surface and having means for interconnecting on the first surface corresponding to the electrical interconnections, the method comprising: (a) depositing a predetermined quantity of an undercoat material having sufficient low expansion fillers to achieve a linear coefficient of thermal expansion (CTE) matching a CTE of the electrical interconnections onto the first surface of one of the chip and the substrate; (b) etching the undercoat material from the first surface of the one of the chip and the substrate until the electrical interconnections or the means for interconnecting are exposed; (c) connecting the electrical interconnections of the chip to the means for interconnecting of the substrate so as to form an electrical interconnection bond therebetween; and (d) heating, reflowing and curing the undercoat material during or after step (c).
Claim 3
Dependent Claim
17 words
The method of claim 1, wherein the chip is connected to the substrate by mass diffusion bonding.
Claim 4
Dependent Claim
13 words
The method of claim 1, wherein the undercoat material is a thermoplastic composition.
Claim 5
Dependent Claim
14 words
The method of claim 1, wherein the undercoat material is a B-stageable thermoset composition.
Claim 6
Dependent Claim
27 words
The method of claim 4, further comprising the step of subjecting the undercoat material to heat prior to the step of connecting the chip to the substrate.
Claim 7
Dependent Claim
20 words
The method of claim 1, wherein the chip is a flip-chip semiconductor device and the electrical interconnections are bumped pads.
Claim 8
Dependent Claim
26 words
The method of claim 6, wherein the bumped pads of the chip are connected to the substrate by a monolithic binary or a ternary metal system.
Claim 9
Dependent Claim
21 words
The method of claim 1 wherein the step of depositing the undercoat material is performed utilizing spinning or spray coating techniques.
Claim 10
Dependent Claim
15 words
The method of claim 1, wherein the undercoat material is etched utilizing plasma etching techniques.
Claim 11
Dependent Claim
22 words
The method of claim 1, wherein the chip is one of a plurality of chips arranged in an array on a wafer.
Claim 12
Dependent Claim
15 words
The method of claim 1, wherein the chip is an active electronic or microelectronic device.
Claim 13
Dependent Claim
15 words
The method of claim 1, wherein the chip is a passive electronic or microelectronic device.
Claim 14
Independent Claim
153 words
A method of fabricating an undercoated chip electrically interconnected to a substrate, the chip having a first and second surface and having electrical interconnections on the first surface, and the substrate having a first and second surface and having means for interconnecting on the first surface corresponding to the electrical interconnections, the method comprising: (a) depositing a predetermined quantity of an undercoat material having sufficient low expansion fillers to achieve a linear coefficient of thermal expansion (CTE) matching a CTE of the electrical interconnections onto predetermined locations on the first surface of one of the chip and the substrate, the predetermined locations not interfering with the electrical interconnections or the means for interconnecting, respectively; (b) connecting the electrical interconnections of the chip to the means for interconnecting of the substrate so as to form an electrical interconnection bond therebetween; and (c) heating, reflowing and curing the undercoat material during or after step (c).
Claim 15
Independent Claim
153 words
A method of fabricating an undercoated chip electrically interconnected to a substrate, the chip having a first and second surface and having electrical interconnections on the first surface, and the substrate having a first and second surface and having means for interconnecting on the first surface corresponding to the electrical interconnections, the method comprising: (a) depositing a predetermined quantity of an undercoat material having sufficient low expansion fillers to achieve a linear coefficient of thermal expansion (CTE) matching a CTE of the electrical interconnections onto predetermined locations on the first surface of one of the chip and the substrate, the predetermined locations not interfering with the electrical interconnections or the means for interconnecting, respectively; (b) connecting the electrical interconnections of the chip to the means for interconnecting of the substrate so as to form an electrical interconnection bond therebetween; and (c) heating, reflowing and curing the undercoat material during or after step (c).
Claim 16
Dependent Claim
14 words
The method of claim 13, wherein the undercoat material is in a preform shape.
Claim 17
Dependent Claim
14 words
The method of claim 13, wherein the undercoat material is in an extruded shape.
Claim 18
Dependent Claim
20 words
The method of claim 13, wherein the step of depositing the undercoat material is performed utilizing a hot-melt extrusion tip.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-03 | 2000-06-03 | 2000-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-03 | 2004-06-03 | 2004-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-03 | 2008-06-03 | 2008-12-03 | $7700.00 | Window Closed / Lapsed |